netdev - Re: Synopsys Ethernet QoS Driver

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Message-ID: <5d59aac4-1616-5316-a624-192b390d1569@st.com>
Date:   Fri, 25 Nov 2016 09:55:39 +0100
From:   Giuseppe CAVALLARO <peppe.cavallaro@...com>
To:     Joao Pinto <Joao.Pinto@...opsys.com>,
        Lars Persson <lars.persson@...s.com>
CC:     Rayagond Kokatanur <rayagond@...avyalabs.com>,
        Rabin Vincent <rabin@....in>, mued dib <kreptor@...il.com>,
        David Miller <davem@...emloft.net>,
        Jeff Kirsher <jeffrey.t.kirsher@...el.com>,
        "jiri@...lanox.com" <jiri@...lanox.com>,
        "saeedm@...lanox.com" <saeedm@...lanox.com>,
        "idosch@...lanox.com" <idosch@...lanox.com>,
        netdev <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "CARLOS.PALMINHA@...opsys.com" <CARLOS.PALMINHA@...opsys.com>,
        Andreas Irestål <andire@...s.com>,
        "alexandre.torgue@...com" <alexandre.torgue@...com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: Synopsys Ethernet QoS Driver

On 11/23/2016 12:43 PM, Joao Pinto wrote:
>> > Rabin Vincent can review and test that the port works properly on our Artpec-chips that use dwc_eth_qos.c today.
>> >
>> > The main porting step is to implement the device tree binding in bindings/net/snps,dwc-qos-ethernet.txt. Also our chip has a strict requirement that the phy is enabled when the SWR reset bit is set (it needs a tx clock to complete the reset).
>> >
>> > - Lars
> Ok, I will do the task.
>
> @Peppe: Agree with the plan?

Agree

peppe