netdev - RE: [PATCH net-next v3 3/4] Documentation: net: phy: Add blurb about RGMII

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Message-ID: <063D6719AE5E284EB5DD2968C1650D6DB022CC81@AcuExch.aculab.com>
Date:   Tue, 29 Nov 2016 13:47:53 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Florian Fainelli' <f.fainelli@...il.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
CC:     "davem@...emloft.net" <davem@...emloft.net>,
        "andrew@...n.ch" <andrew@...n.ch>,
        "sf84@...oste.net" <sf84@...oste.net>,
        "martin.blumenstingl@...glemail.com" 
        <martin.blumenstingl@...glemail.com>,
        "mans@...sr.com" <mans@...sr.com>,
        "alexandre.torgue@...com" <alexandre.torgue@...com>,
        "peppe.cavallaro@...com" <peppe.cavallaro@...com>,
        "timur@...eaurora.org" <timur@...eaurora.org>,
        "jbrunet@...libre.com" <jbrunet@...libre.com>
Subject: RE: [PATCH net-next v3 3/4] Documentation: net: phy: Add blurb
 about RGMII

From: Florian Fainelli
> Sent: 28 November 2016 02:45
> RGMII is a recurring source of pain for people with Gigabit Ethernet
> hardware since it may require PHY driver and MAC driver level
> configuration hints. Document what are the expectations from PHYLIB and
> what options exist.
...
> + * PHY_INTERFACE_MODE_RGMII_TXID: the PHY should insert an internal delay
> +   for the transmit data lines (TXD[3:0]) processed by the PHY device
> +
> + * PHY_INTERFACE_MODE_RGMII_RXID: the PHY should insert an internal delay
> +   for the receive data lines (RXD[3:0]) processed by the PHY device

These delays are subtly different, so the texts shouldn't really be the same.
I think the clock is delayed before latching the TX data and the RX data gets
delayed from the clock.

...
> + * Switching to lower speeds such as 10/100Mbits/sec makes the problem go away
> +   (since there is enough setup/hold time in that case)

The setup/hold times aren't directly affected by the lower speed.
So something else is going on.
Possibly the data is changed on one edge and sampled on the other at lower
speeds, but changes every clock edge at 1Gb.

	David