netdev - RE: [Open-FCoE] [PATCH RFC net-next 1/5] qed: Add support for hardware offloaded FCoE.

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Message-ID: <BL2PR07MB2306CCCE99C9CEB761ADF5A08D6B0@BL2PR07MB2306.namprd07.prod.outlook.com>
Date:   Thu, 29 Dec 2016 17:28:36 +0000
From:   "Mintz, Yuval" <Yuval.Mintz@...ium.com>
To:     Hannes Reinecke <hare@...e.de>,
        "Dupuis, Chad" <Chad.Dupuis@...ium.com>,
        "martin.petersen@...cle.com" <martin.petersen@...cle.com>
CC:     "fcoe-devel@...n-fcoe.org" <fcoe-devel@...n-fcoe.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "Dept-Eng QLogic Storage Upstream" 
        <QLogic-Storage-Upstream@...ium.com>,
        "linux-scsi@...r.kernel.org" <linux-scsi@...r.kernel.org>
Subject: RE: [Open-FCoE] [PATCH RFC net-next 1/5] qed: Add support for
 hardware offloaded FCoE.

> > +struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
> > +	union fcoe_cleanup_addr_exp_ro_union
> cleanup_addr_exp_ro_union;
> > +	__le16 flags;
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK
> 0x7
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT      0
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK
> 0x1
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT
> 3
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK
> 0x1
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT       4
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK
> 0x1
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT      5
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK
> 0x1
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT
> 6
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MAS
> K   0x1
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT
> 7
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK
> 0x3
> > +#define
> FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT       8
> > +#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK
> 0x3F
> > +#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT
> 10
> 
> A very odd way of defining a bitfield ...
> Why not use a 'normal' bitfield here?

This is the format of our generated firmware HSI; We already have
Thousands of definitions using this same format.