netdev - Re: [PATCH] stmmac: Enable Clause 45 PHYs in GAMC4

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Message-Id: <20170104.141141.514392926320888488.davem@davemloft.net>
Date:   Wed, 04 Jan 2017 14:11:41 -0500 (EST)
From:   David Miller <davem@...emloft.net>
To:     Joao.Pinto@...opsys.com
Cc:     hock.leong.kweh@...el.com, netdev@...r.kernel.org
Subject: Re: [PATCH] stmmac: Enable Clause 45 PHYs in GAMC4

From: Joao Pinto <Joao.Pinto@...opsys.com>
Date: Wed,  4 Jan 2017 14:35:26 +0000

> The eQOS IP Core (best known in stmmac as gmac4) has a register that must be
> set if using a Clause 45 PHY. If this register is not set, the PHY won't work.
> This patch will have no impact in setups using Clause 22 PHYs.
> 
> Signed-off-by: Joao Pinto <jpinto@...opsys.com>

Why don't you set this bit for MDIO reads as well?

If it isn't necessary for reads, you have to explain this in your commit
message otherwise people will wonder the same thing I did when they see
that only writes are handled.

Thanks.