netdev - Re: [net, 3/6] net: korina: increase tx/rx ring sizes

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Message-ID: <1484680816.13165.73.camel@edumazet-glaptop3.roam.corp.google.com>
Date:   Tue, 17 Jan 2017 11:20:16 -0800
From:   Eric Dumazet <eric.dumazet@...il.com>
To:     Roman Yeryomin <leroi.lists@...il.com>
Cc:     David Miller <davem@...emloft.net>, netdev@...r.kernel.org
Subject: Re: [net, 3/6] net: korina: increase tx/rx ring sizes

On Tue, 2017-01-17 at 20:27 +0200, Roman Yeryomin wrote:
> On 17 January 2017 at 19:58, David Miller <davem@...emloft.net> wrote:
> > From: Roman Yeryomin <leroi.lists@...il.com>
> > Date: Tue, 17 Jan 2017 19:32:36 +0200
> >
> >> Having larger ring sizes almost eliminates rx fifo overflow, thus improving performance.
> >> This patch reduces rx overflow occurence by approximately 1000 times (from ~25k down to ~25 times per 3M frames)
> >
> > Those numbers don't mean much without full context.
> >
> > What kind of system, what kind of traffic, and over what kind of link?
> 
> MIPS rb532 board, TCP iperf3 test over 100M link, NATed speed ~55Mbps.
> I can do more tests and provide more precise numbers, if needed.

Note that at 100M,  64 rx descriptors have a 8 ms max latency.

Switching to 256 also multiply by 4 the latency -> 32 ms latency.

Presumably switching to NAPI and GRO would avoid the latency increase
and save a lot of cpu cycles for a MIPS board.