netdev - RE: [net-next 2/8] net/mlx5: Configure cache line size for start and end padding

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Message-ID: <063D6719AE5E284EB5DD2968C1650D6DB0277BC4@AcuExch.aculab.com>
Date:   Wed, 1 Feb 2017 11:12:42 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Saeed Mahameed' <saeedm@...lanox.com>,
        "David S. Miller" <davem@...emloft.net>
CC:     "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        Daniel Jurgens <danielj@...lanox.com>
Subject: RE: [net-next 2/8] net/mlx5: Configure cache line size for start
 and end padding

From: Saeed Mahameed
> Sent: 31 January 2017 20:59
> From: Daniel Jurgens <danielj@...lanox.com>
> 
> There is a hardware feature that will pad the start or end of a DMA to
> be cache line aligned to avoid RMWs on the last cache line. The default
> cache line size setting for this feature is 64B. This change configures
> the hardware to use 128B alignment on systems with 128B cache lines.

What guarantees that the extra bytes are actually inside the receive skb's
head and tail room?

	David