netdev - Re: [PATCH v3 net-next 4/9] net: stmicro: mtl rx queue enabled as dcb or avb

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Message-ID: <713f3c43-d57f-fb37-1fb6-24f5c13d0958@cogentembedded.com>
Date:   Thu, 9 Mar 2017 15:01:39 +0300
From:   Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
To:     Joao Pinto <Joao.Pinto@...opsys.com>, davem@...emloft.net
Cc:     peppe.cavallaro@...com, alexandre.torgue@...com,
        niklas.cassel@...s.com, netdev@...r.kernel.org
Subject: Re: [PATCH v3 net-next 4/9] net: stmicro: mtl rx queue enabled as dcb
 or avb

Hello!

On 03/09/2017 02:03 PM, Joao Pinto wrote:

> This patch introduces the enabling of RX queues as DCB or as AVB based on
> configuration.
>
> Signed-off-by: Joao Pinto <jpinto@...opsys.com>
[...]
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
> index 6f59751..04d0fa3 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
> @@ -59,13 +59,17 @@ static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
>  	writel(value, ioaddr + GMAC_INT_EN);
>  }
>
> -static void dwmac4_rx_queue_enable(struct mac_device_info *hw, u32 queue)
> +static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
> +				   u8 mode, u32 queue)
>  {
>  	void __iomem *ioaddr = hw->pcsr;
>  	u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
>
>  	value &= GMAC_RX_QUEUE_CLEAR(queue);
> -	value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
> +	if (mode == MTL_RX_AVB)
> +		value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
> +	else if (mode == MTL_RX_DCB)
> +		value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);

    *switch*, maybe?

[...]
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 1ad6957..17faa1f 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -1256,19 +1256,14 @@ static void free_dma_desc_resources(struct stmmac_priv *priv)
>   */
>  static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
>  {
> -	int rx_count = priv->dma_cap.number_rx_queues;
> +	u32 rx_queues_count = priv->plat->rx_queues_to_use;
>  	int queue = 0;

    It's now set to 0 right below, in the *for* statement. So this initializer 
seems useless.

> +	u8 mode = 0;
>
> -	/* If GMAC does not have multiple queues, then this is not necessary*/
> -	if (rx_count == 1)
> -		return;
> -
> -	/**
> -	 *  If the core is synthesized with multiple rx queues / multiple
> -	 *  dma channels, then rx queues will be disabled by default.
> -	 *  For now only rx queue 0 is enabled.
> -	 */
> -	priv->hw->mac->rx_queue_enable(priv->hw, queue);
> +	for (queue = 0; queue < rx_queues_count; queue++) {
> +		mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
> +		priv->hw->mac->rx_queue_enable(priv->hw, mode, queue);
> +	}
>  }
>
>  /**

MBR, Sergei