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Date:   Tue, 14 Mar 2017 00:11:27 +0800
From:   <sean.wang@...iatek.com>
To:     <andrew@...n.ch>, <f.fainelli@...il.com>,
        <vivien.didelot@...oirfairelinux.com>, <matthias.bgg@...il.com>,
        <robh+dt@...nel.org>, <mark.rutland@....com>
CC:     <devicetree@...r.kernel.org>, <netdev@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-mediatek@...ts.infradead.org>, <davem@...emloft.net>,
        <sean.wang@...iatek.com>, <Landen.Chao@...iatek.com>,
        <keyhaede@...il.com>, <objelf@...il.com>
Subject: [PATCH net-next 3/4] net-next: ethernet: mediatek: add CDM able to recognize the tag for DSA

From: Sean Wang <sean.wang@...iatek.com>

Allowing CDM can recognize these packets with carrying port-distinguishing
tag when CONFIG_NET_DSA_TAG_MTK is enabled. Otherwise, these packets will
be dropped by CDM ingress.

Signed-off-by: Sean Wang <sean.wang@...iatek.com>
Signed-off-by: Landen Chao <Landen.Chao@...iatek.com>
---
 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 ++++++++
 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 3dd8788..19944e0 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1848,6 +1848,14 @@ static int mtk_hw_init(struct mtk_eth *eth)
 	/* GE2, Force 1000M/FD, FC ON */
 	mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
 
+#if defined(CONFIG_NET_DSA_TAG_MTK)
+	/* Tell CDMQ to parse the MTK special tag from CPU  */
+	/* QDMA Tx Use CDMQ */
+	u32 val2 = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
+
+	mtk_w32(eth, val2 | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
+#endif
+
 	/* Enable RX VLan Offloading */
 	mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
 
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 99b1c8e..79606db 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -70,11 +70,16 @@
 /* Frame Engine Interrupt Grouping Register */
 #define MTK_FE_INT_GRP		0x20
 
+/* CDMP Ingress Control Register */
+#define MTK_CDMQ_IG_CTRL	0x1400
+#define MTK_CDMQ_STAG_EN	BIT(0)
+
 /* CDMP Exgress Control Register */
 #define MTK_CDMP_EG_CTRL	0x404
 
 /* GDM Exgress Control Register */
 #define MTK_GDMA_FWD_CFG(x)	(0x500 + (x * 0x1000))
+#define MTK_GDMA_STAG_EN	BIT(24)
 #define MTK_GDMA_ICS_EN		BIT(22)
 #define MTK_GDMA_TCS_EN		BIT(21)
 #define MTK_GDMA_UCS_EN		BIT(20)
-- 
1.9.1

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