netdev - Re: [PATCH net-next] cxgb4: Update IngPad and IngPack values

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Date:   Wed, 22 Mar 2017 10:54:00 -0700 (PDT)
From:   David Miller <davem@...emloft.net>
To:     ganeshgr@...lsio.com
Cc:     netdev@...r.kernel.org, nirranjan@...lsio.com, arjun@...lsio.com,
        leedom@...lsio.com
Subject: Re: [PATCH net-next] cxgb4: Update IngPad and IngPack values

From: Ganesh Goudar <ganeshgr@...lsio.com>
Date: Mon, 20 Mar 2017 14:22:38 +0530

> From: Arjun Vynipadath <arjun@...lsio.com>
> 
> We are using the smallest padding boundary (8 bytes), which isn't
> smaller than the Memory Controller Read/Write Size
> 
> We get best performance in 100G when the Packing Boundary is a multiple
> of the Maximum Payload Size. Its related to inefficient chopping of DMA
> packets by PCIe, that causes more overhead on bus. So driver is helping
> by making the starting address alignment to be MPS size.
> 
> We will try to determine PCIE MaxPayloadSize capabiltiy  and set
> IngPackBoundary based on this value. If cache line size is greater than
> MPS or determinig MPS fails, we will use cache line size to determine
> IngPackBoundary(as before).
> 
> Signed-off-by: Arjun Vynipadath <arjun@...lsio.com>
> Signed-off-by: Casey Leedom <leedom@...lsio.com>
> Signed-off-by: Ganesh Goudar <ganeshgr@...lsio.com>

Applied, thank you.