netdev - Re: [PATCH v3] smsc95xx: Add comments to the registers definition

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Message-ID: <20170412160123.zhzg67m4rpzcsmap@SMX-2>
Date:   Wed, 12 Apr 2017 18:01:23 +0200
From:   martin@...terwald.eu
To:     Woojung.Huh@...rochip.com
Cc:     davem@...emloft.net, andrew@...n.ch, steve.glendinning@...well.net,
        UNGLinuxDriver@...rochip.com, netdev@...r.kernel.org,
        linux-usb@...r.kernel.org
Subject: Re: [PATCH v3] smsc95xx: Add comments to the registers definition

On 12/04/17 14:25, Woojung.Huh@...rochip.com wrote:
> > +/* LED General Purpose IO Configuration Register */
> > +#define LED_GPIO_CFG		(0x24)
> > +#define LED_GPIO_CFG_SPD_LED	(0x01000000)	/* GPIO2 as SPD LED
> > */
> > +#define LED_GPIO_CFG_LNK_LED	(0x00100000)	/* GPIO1 as LNK LED
> > */
> > +#define LED_GPIO_CFG_FDX_LED	(0x00010000)	/* GPIO0 as FDX LED
> > */
> Because comments are one of main reason for this patch.
> It is GPIO 10, 9 & 8.
> 
> Woojung

Hello Woojung,

I based my comments on the datasheet. For the LED_GPIO_CFG register, the
datasheet says:
> This register configures the external GPIO[2:0] pins.

QFN package description also indicates GPIOs 0, 1 & 2.
As an example for the LAN9514, pin 22 of the QFN indicates:
> nSPD_LED/GPIO2

In LED_GPIO_CFG register, GPCTL2 description indicates:
> The value of this field determines the function of the external GPIO2
> pin as follows

Do you confirm it's actually GPIO 10, 9 and 8?
I think I may have misunderstood something.


While we are here, could you indicate the meaning of the bit 2 of
HW_CFG register (it's named HW_CFG_PSEL_)? It's the only bit I didn't
succeed to comment because I didn't find it in the datasheet.
I will then add it to the patch!

I'm also wondering what the meaning of STRAP_STATUS is. I could also
comment it if you or Steve can provide the information.


Thank you!

Martin