netdev - Re: [for-next 4/6] net/mlx5: FPGA, Add basic support for Innova

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Message-ID: <20170607154858.GA30124@obsidianresearch.com>
Date:   Wed, 7 Jun 2017 09:48:58 -0600
From:   Jason Gunthorpe <jgunthorpe@...idianresearch.com>
To:     Saeed Mahameed <saeedm@....mellanox.co.il>
Cc:     Ilan Tayari <ilant@...lanox.com>,
        Alexei Starovoitov <alexei.starovoitov@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Doug Ledford <dledford@...hat.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
        "jsorensen@...com" <jsorensen@...com>,
        Andy Shevchenko <andy.shevchenko@...il.com>,
        "linux-fpga@...r.kernel.org" <linux-fpga@...r.kernel.org>,
        Alan Tull <atull@...nsource.altera.com>,
        "yi1.li@...ux.intel.com" <yi1.li@...ux.intel.com>,
        Boris Pismenny <borisp@...lanox.com>
Subject: Re: [for-next 4/6] net/mlx5: FPGA, Add basic support for Innova

On Wed, Jun 07, 2017 at 07:16:42AM +0300, Saeed Mahameed wrote:
> On Tue, Jun 6, 2017 at 7:17 PM, Jason Gunthorpe
> <jgunthorpe@...idianresearch.com> wrote:
> > On Tue, Jun 06, 2017 at 06:52:15AM +0000, Ilan Tayari wrote:
> >
> >> So neither the host stack nor the network are aware of them.
> >> They exist momentarily only on the internal traces on the board and not
> >> anywhere else.
> >
> > Is that really true? If you are creating rocee QPs' then the RDMA
> > stack sees this stuff and now we have buried a RDMA ULP inside an
> > ethernet driver which seems really wonky..
> 
> It is not an ethernet driver, mlx5_core provides both RDMA and
> ethernet interfaces to both mlx5_ib and the mlx5e netdevice.
> 
> so it is perfectly capable of creating QPs on its own, after all it is
> the one creating QPs for the RDMA stack :).
> 
> rdma_create_qp->mlx5_ib_create_qp->mlx5_core_create_qp.

Wait, so you built a RDMA ULP inside your driver without using the
RDMA API?

This keep getting more ugly :(

What about security? What if user space sends some raw packets to the
FPGA - can it reprogram the ISPEC settings or worse?

Jason