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Date: Thu, 15 Jun 2017 11:19:28 +0100 From: Måns Rullgård <mans@...sr.com> To: Mason <slash.tmp@...e.fr> Cc: Florian Fainelli <f.fainelli@...il.com>, netdev <netdev@...r.kernel.org>, Andrew Lunn <andrew@...n.ch>, Thibaud Cornic <thibaud_cornic@...madesigns.com> Subject: Re: Toggling link state breaks network connectivity Mason <slash.tmp@...e.fr> writes: > [ 33.393332] ENTER nb8800_stop > [ 33.421731] nb8800_mdio_write: reg=9 val=0200 # by genphy_config_aneg() > [ 33.444062] nb8800_mdio_write: reg=0 val=1200 # by genphy_restart_aneg() > [ 33.466411] nb8800_mdio_write: reg=18 val=0000 # by at803x_config_intr() from phy_stop() Those are from the phy_stop() call. The following is the ridiculous dance required to stop rx dma in nb8800_dma_stop(): > [ 33.488859] ++ETH++ gw8 0xf0026004 0x03 # ETH_MAC_CORE_RECEIVE_CONTROL Disable address filter. > [ 33.492805] ++ETH++ gw8 0xf0026044 0x04 # ETH_MAC_CORE_MAC_MODE *WHY ??* Enable loopback. > [ 33.496748] ++ETH++ gw32 0xf002610c 0x9dcac000 \ > [ 33.501217] ++ETH++ gw32 0xf0026100 0x000002ff | Send frame. > [ 33.505750] ++ETH++ gw32 0xf0026104 0x00000004 | IRQ? > [ 33.510213] ++ETH++ gw32 0xf0026204 0x00000004 | > [ 33.514674] ++ETH++ gw32 0xf0026218 0x003cc4a4 | > [ 33.519146] ++ETH++ gw32 0xf0026104 0x00000001 / Handle resulting interrupt(s). > [ 33.605719] ++ETH++ gw32 0xf002610c 0x9dcac000 \ > [ 33.610187] ++ETH++ gw32 0xf0026100 0x000002ff | Send frame. > [ 33.614717] ++ETH++ gw32 0xf0026104 0x00000004 | ANOTHER IRQ? > [ 33.619178] ++ETH++ gw32 0xf0026204 0x00000004 | > [ 33.623637] ++ETH++ gw32 0xf0026218 0x003cc4a4 | > [ 33.628106] ++ETH++ gw32 0xf0026104 0x00000001 / Handle interrupt(s). > [ 33.714689] ++ETH++ gw32 0xf002610c 0x9dcac000 | > [ 33.719156] ++ETH++ gw32 0xf0026100 0x000002ff | ANOTHER IRQ? Send frame. > [ 33.723686] ++ETH++ gw32 0xf0026104 0x00000004 | Handle tx interrupt. > [ 33.724625] ++ETH++ gw8 0xf0026004 0x23 # ETH_MAC_CORE_RECEIVE_CONTROL Enable address filter. > [ 33.724627] ++ETH++ gw8 0xf0026044 0x00 # ETH_MAC_CORE_MAC_MODE *AGAIN ??* Disable loopback. > [ 33.724640] ++ETH++ gw32 0xf002620c 0x9de36000 >From nb8800_dma_reset(). > [ 33.724642] ++ETH++ gw8 0xf0026004 0x22 # ETH_MAC_CORE_RECEIVE_CONTROL AGAIN Disable rx. > [ 33.724644] ++ETH++ gw8 0xf0026000 0x1c # ETH_MAC_CORE_TRANSMIT_CONTROL Disable tx. > [ 33.724690] nb8800_mdio_write: reg=18 val=0000 # by at803x_config_intr() from phy_disable_interrupts() > [ 33.724913] nb8800_mdio_write: reg=0 val=1800 # by at803x_suspend() from phy_suspend() > [ 33.819562] ++ETH++ gw32 0xf0026204 0x00000004 > [ 33.824021] ++ETH++ gw32 0xf0026218 0x003cc4a4 Handle rx interrupt, probably from the last loopback frame sent earlier. > [ 33.828518] EXIT nb8800_stop Now I did notice one thing. When the interrupts from the loopback frames are handled, the rx interrupt is all but disabled for NAPI poll mode. Of course, NAPI isn't active, so the rx interrupt never gets re-enabled. We should probably do this in ndo_open just to be sure. Try this patch: diff --git a/drivers/net/ethernet/aurora/nb8800.c b/drivers/net/ethernet/aurora/nb8800.c index e078d8da978c..f968468076b9 100644 --- a/drivers/net/ethernet/aurora/nb8800.c +++ b/drivers/net/ethernet/aurora/nb8800.c @@ -969,6 +969,7 @@ static int nb8800_open(struct net_device *dev) if (err) goto err_free_dma; + nb8800_writel(priv, NB8800_RX_ITR, priv->rx_itr_irq); nb8800_mac_rx(dev, true); nb8800_mac_tx(dev, true); -- Måns Rullgård
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