netdev - Re: [PATCH v3 2/2] ravb: add workaround for clock when resuming with WoL enabled

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Message-ID: <4e0cd03e-a2f0-2a41-7c66-903a0eed03a6@cogentembedded.com>
Date:   Tue, 1 Aug 2017 16:27:17 +0300
From:   Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
To:     Niklas Söderlund 
        <niklas.soderlund+renesas@...natech.se>
Cc:     Geert Uytterhoeven <geert@...ux-m68k.org>, netdev@...r.kernel.org,
        linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v3 2/2] ravb: add workaround for clock when resuming with
 WoL enabled

On 08/01/2017 01:14 PM, Niklas Söderlund wrote:

> The renesas-cpg-mssr clock driver are not yet aware of PSCI sleep where
> power is cut to the SoC. When resuming from this state with WoL enabled
> the enable count of the ravb clock is 1 and the clock driver thinks the
> clock is already on when PM core enables the clock and increments the
> enable count to 2. This will result in the ravb driver failing to talk
> to the hardware since the module clock is off. Work around this by
> forcing the enable count to 0 and then back to 2 when resuming with WoL
> enabled.
> 
> This workaround should be reverted once the renesas-cpg-mssr clock
> driver becomes aware of this PSCI sleep behavior.
> 
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@...natech.se>

Acked-by: Sergei Shtylyov <sergei.shtylyov@...entembedded.com>

MBR, Sergei