netdev - [PATCH v6 06/11] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac

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Message-Id: <20170927073414.17361-7-clabbe.montjoie@gmail.com>
Date:   Wed, 27 Sep 2017 09:34:09 +0200
From:   Corentin Labbe <clabbe.montjoie@...il.com>
To:     robh+dt@...nel.org, mark.rutland@....com,
        maxime.ripard@...e-electrons.com, wens@...e.org,
        linux@...linux.org.uk, catalin.marinas@....com,
        will.deacon@....com, peppe.cavallaro@...com,
        alexandre.torgue@...com, andrew@...n.ch, f.fainelli@...il.com,
        frowand.list@...il.com
Cc:     netdev@...r.kernel.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-sunxi@...glegroups.com,
        Corentin Labbe <clabbe.montjoie@...il.com>
Subject: [PATCH v6 06/11] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac

Since dwmac-sun8i could use either an integrated PHY or an external PHY
(which could be at same MDIO address), we need to represent this selection
by a MDIO switch.

Signed-off-by: Corentin Labbe <clabbe.montjoie@...il.com>
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 +++++++++++++++++++++++++------
 1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 3b7d953429a6..a8e9b8f378ba 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -422,14 +422,33 @@
 			#size-cells = <0>;
 			status = "disabled";
 
-			mdio: mdio {
+			mdio0: mdio {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				int_mii_phy: ethernet-phy@1 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <1>;
-					clocks = <&ccu CLK_BUS_EPHY>;
-					resets = <&ccu RST_BUS_EPHY>;
+				compatible = "snps,dwmac-mdio";
+
+				mdio-mux {
+					compatible = "mdio-mux";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					/* Only one MDIO is usable at the time */
+					internal_mdio: mdio@1 {
+						reg = <1>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						int_mii_phy: ethernet-phy@1 {
+							compatible = "ethernet-phy-ieee802.3-c22";
+							reg = <1>;
+							clocks = <&ccu CLK_BUS_EPHY>;
+							resets = <&ccu RST_BUS_EPHY>;
+							phy-is-integrated;
+						};
+					};
+					mdio: mdio@2 {
+						reg = <2>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
 				};
 			};
 		};
-- 
2.13.5