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Message-ID: <40c73797-6f4c-357c-bdc3-7a9aa0ad8793@gmail.com>
Date: Tue, 21 Nov 2017 17:39:13 -0800
From: Florian Fainelli <f.fainelli@...il.com>
To: netdev@...r.kernel.org
Cc: davem@...emloft.net, andrew@...n.ch,
vivien.didelot@...oirfairelinux.com
Subject: Re: [PATCH] net: dsa: bcm_sf2: Clear IDDQ_GLOBAL_PWR bit for PHY
On 11/21/2017 05:37 PM, Florian Fainelli wrote:
> From: Florian Fainelli <florian.fainelli@...adcom.com>
>
> The PHY on BCM7278 has an additional bit that needs to be cleared:
> IDDQ_GLOBAL_PWR, without doing this, the PHY remains stuck in reset out
> of suspend/resume cycles.
>
> refs #SWLINUX-4599
Meh, sorry David, I had forgotten to sanitize the patch for upstream
inclusion, I just sent a corrected version.
>
> Fixes: 1ad948be42b4 ("net: dsa: bcm_sf2: Add support for BCM7278 integrated switch")
> Signed-off-by: Florian Fainelli <florian.fainelli@...adcom.com>
> ---
> drivers/net/dsa/bcm_sf2.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
> index 09b48f9b4091..12b921d1c54b 100644
> --- a/drivers/net/dsa/bcm_sf2.c
> +++ b/drivers/net/dsa/bcm_sf2.c
> @@ -214,7 +214,7 @@ static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
> reg = reg_readl(priv, REG_SPHY_CNTRL);
> if (enable) {
> reg |= PHY_RESET;
> - reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
> + reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
> reg_writel(priv, reg, REG_SPHY_CNTRL);
> udelay(21);
> reg = reg_readl(priv, REG_SPHY_CNTRL);
>
--
Florian
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