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Message-Id: <20171201231807.25266-5-david.daney@cavium.com>
Date: Fri, 1 Dec 2017 15:18:04 -0800
From: David Daney <david.daney@...ium.com>
To: linux-mips@...ux-mips.org, ralf@...ux-mips.org,
James Hogan <james.hogan@...s.com>, netdev@...r.kernel.org,
"David S. Miller" <davem@...emloft.net>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>
Cc: linux-kernel@...r.kernel.org,
"Steven J. Hill" <steven.hill@...ium.com>,
devicetree@...r.kernel.org, Andrew Lunn <andrew@...n.ch>,
Florian Fainelli <f.fainelli@...il.com>,
Philippe Ombredanne <pombredanne@...b.com>,
Carlos Munoz <cmunoz@...ium.com>,
"Steven J . Hill" <Steven.Hill@...ium.com>,
David Daney <david.daney@...ium.com>
Subject: [PATCH v5 net-next,mips 4/7] MIPS: Octeon: Add Free Pointer Unit (FPA) support.
From: Carlos Munoz <cmunoz@...ium.com>
>From the hardware user manual: "The FPA is a unit that maintains
pools of pointers to free L2/DRAM memory. To provide QoS, the pools
are referenced indirectly through 1024 auras. Both core software
and hardware units allocate and free pointers."
Signed-off-by: Carlos Munoz <cmunoz@...ium.com>
Signed-off-by: Steven J. Hill <Steven.Hill@...ium.com>
Signed-off-by: David Daney <david.daney@...ium.com>
---
arch/mips/cavium-octeon/Kconfig | 8 +
arch/mips/cavium-octeon/Makefile | 1 +
arch/mips/cavium-octeon/octeon-fpa3.c | 363 ++++++++++++++++++++++++++++++++++
arch/mips/include/asm/octeon/octeon.h | 13 ++
4 files changed, 385 insertions(+)
create mode 100644 arch/mips/cavium-octeon/octeon-fpa3.c
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 204a1670fd9b..ce469f982134 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -87,4 +87,12 @@ config OCTEON_ILM
To compile this driver as a module, choose M here. The module
will be called octeon-ilm
+config OCTEON_FPA3
+ tristate "Octeon III fpa driver"
+ help
+ This option enables a Octeon III driver for the Free Pool Unit (FPA).
+ The FPA is a hardware unit that manages pools of pointers to free
+ L2/DRAM memory. This driver provides an interface to reserve,
+ initialize, and fill fpa pools.
+
endif # CAVIUM_OCTEON_SOC
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 28c0bb75d1a4..9d547c2cd77d 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_MTD) += flash_setup.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o
obj-$(CONFIG_USB) += octeon-usb.o
+obj-$(CONFIG_OCTEON_FPA3) += octeon-fpa3.o
diff --git a/arch/mips/cavium-octeon/octeon-fpa3.c b/arch/mips/cavium-octeon/octeon-fpa3.c
new file mode 100644
index 000000000000..3f0c10e9d915
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon-fpa3.c
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the Octeon III Free Pool Unit (fpa).
+ *
+ * Copyright (C) 2015-2017 Cavium, Inc.
+ */
+
+#include <linux/module.h>
+
+#include <asm/octeon/octeon.h>
+
+
+/* Registers are accessed via xkphys */
+#define SET_XKPHYS (1ull << 63)
+#define NODE_OFFSET 0x1000000000ull
+#define SET_NODE(node) ((node) * NODE_OFFSET)
+
+#define FPA_BASE 0x1280000000000ull
+#define SET_FPA_BASE(node) (SET_XKPHYS + SET_NODE(node) + FPA_BASE)
+
+#define FPA_GEN_CFG(n) (SET_FPA_BASE(n) + 0x00000050)
+
+#define FPA_POOLX_CFG(n, p) (SET_FPA_BASE(n) + (p<<3) + 0x10000000)
+#define FPA_POOLX_START_ADDR(n, p) (SET_FPA_BASE(n) + (p<<3) + 0x10500000)
+#define FPA_POOLX_END_ADDR(n, p) (SET_FPA_BASE(n) + (p<<3) + 0x10600000)
+#define FPA_POOLX_STACK_BASE(n, p) (SET_FPA_BASE(n) + (p<<3) + 0x10700000)
+#define FPA_POOLX_STACK_END(n, p) (SET_FPA_BASE(n) + (p<<3) + 0x10800000)
+#define FPA_POOLX_STACK_ADDR(n, p) (SET_FPA_BASE(n) + (p<<3) + 0x10900000)
+
+#define FPA_AURAX_POOL(n, a) (SET_FPA_BASE(n) + (a<<3) + 0x20000000)
+#define FPA_AURAX_CFG(n, a) (SET_FPA_BASE(n) + (a<<3) + 0x20100000)
+#define FPA_AURAX_CNT(n, a) (SET_FPA_BASE(n) + (a<<3) + 0x20200000)
+#define FPA_AURAX_CNT_LIMIT(n, a) (SET_FPA_BASE(n) + (a<<3) + 0x20400000)
+#define FPA_AURAX_CNT_THRESHOLD(n, a) (SET_FPA_BASE(n) + (a<<3) + 0x20500000)
+#define FPA_AURAX_POOL_LEVELS(n, a) (SET_FPA_BASE(n) + (a<<3) + 0x20700000)
+#define FPA_AURAX_CNT_LEVELS(n, a) (SET_FPA_BASE(n) + (a<<3) + 0x20800000)
+
+static inline u64 oct_csr_read(u64 addr)
+{
+ return __raw_readq((void __iomem *)addr);
+}
+
+static inline void oct_csr_write(u64 data, u64 addr)
+{
+ __raw_writeq(data, (void __iomem *)addr);
+}
+
+static DEFINE_MUTEX(octeon_fpa3_lock);
+
+static int get_num_pools(void)
+{
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 64;
+ if (OCTEON_IS_MODEL(OCTEON_CNF75XX) || OCTEON_IS_MODEL(OCTEON_CN73XX))
+ return 32;
+ return 0;
+}
+
+static int get_num_auras(void)
+{
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 1024;
+ if (OCTEON_IS_MODEL(OCTEON_CNF75XX) || OCTEON_IS_MODEL(OCTEON_CN73XX))
+ return 512;
+ return 0;
+}
+
+/**
+ * octeon_fpa3_init() - Initialize the fpa to default values.
+ * @node: Node of fpa to initialize.
+ *
+ * Return: 0 if successful.
+ * < 0 for error codes.
+ */
+int octeon_fpa3_init(int node)
+{
+ static bool init_done[2];
+ u64 data;
+ int aura_cnt, i;
+
+ mutex_lock(&octeon_fpa3_lock);
+
+ if (init_done[node])
+ goto done;
+
+ aura_cnt = get_num_auras();
+ for (i = 0; i < aura_cnt; i++) {
+ oct_csr_write(0x100000000ull, FPA_AURAX_CNT(node, i));
+ oct_csr_write(0xfffffffffull, FPA_AURAX_CNT_LIMIT(node, i));
+ oct_csr_write(0xffffffffeull, FPA_AURAX_CNT_THRESHOLD(node, i));
+ }
+
+ data = oct_csr_read(FPA_GEN_CFG(node));
+ data &= ~GENMASK_ULL(9, 4);
+ data |= 3 << 4;
+ oct_csr_write(data, FPA_GEN_CFG(node));
+
+ init_done[node] = 1;
+ done:
+ mutex_unlock(&octeon_fpa3_lock);
+ return 0;
+}
+EXPORT_SYMBOL(octeon_fpa3_init);
+
+/**
+ * octeon_fpa3_pool_init() - Initialize a pool.
+ * @node: Node to initialize pool on.
+ * @pool_num: Requested pool number (-1 for don't care).
+ * @pool: Updated with the initialized pool number.
+ * @pool_stack: Updated with the base of the memory allocated for the pool
+ * stack.
+ * @num_ptrs: Number of pointers to allocated on the stack.
+ *
+ * Return: 0 if successful.
+ * < 0 for error codes.
+ */
+int octeon_fpa3_pool_init(int node, int pool_num, int *pool,
+ void **pool_stack, int num_ptrs)
+{
+ struct global_resource_tag tag;
+ char buf[16];
+ u64 pool_stack_start, pool_stack_end, data;
+ int stack_size, rc = 0;
+
+ mutex_lock(&octeon_fpa3_lock);
+
+ strncpy((char *)&tag.lo, "cvm_pool", 8);
+ snprintf(buf, 16, "_%d......", node);
+ memcpy(&tag.hi, buf, 8);
+
+ res_mgr_create_resource(tag, get_num_pools());
+ *pool = res_mgr_alloc(tag, pool_num, true);
+ if (*pool < 0) {
+ rc = -ENODEV;
+ goto error;
+ }
+
+ oct_csr_write(0, FPA_POOLX_CFG(node, *pool));
+ oct_csr_write(128, FPA_POOLX_START_ADDR(node, *pool));
+ oct_csr_write(GENMASK_ULL(41, 7), FPA_POOLX_END_ADDR(node, *pool));
+
+ stack_size = (DIV_ROUND_UP(num_ptrs, 29) + 1) * 128;
+ *pool_stack = kmalloc_node(stack_size, GFP_KERNEL, node);
+ if (!*pool_stack) {
+ pr_err("Failed to allocate pool stack memory pool=%d\n",
+ pool_num);
+ rc = -ENOMEM;
+ goto error_stack;
+ }
+
+ pool_stack_start = virt_to_phys(*pool_stack);
+ pool_stack_end = round_down(pool_stack_start + stack_size, 128);
+ pool_stack_start = round_up(pool_stack_start, 128);
+ oct_csr_write(pool_stack_start, FPA_POOLX_STACK_BASE(node, *pool));
+ oct_csr_write(pool_stack_start, FPA_POOLX_STACK_ADDR(node, *pool));
+ oct_csr_write(pool_stack_end, FPA_POOLX_STACK_END(node, *pool));
+
+ data = (2 << 3) | BIT(0);
+ oct_csr_write(data, FPA_POOLX_CFG(node, *pool));
+
+ mutex_unlock(&octeon_fpa3_lock);
+ return 0;
+
+error_stack:
+ res_mgr_free(tag, *pool);
+error:
+ mutex_unlock(&octeon_fpa3_lock);
+ return rc;
+}
+EXPORT_SYMBOL(octeon_fpa3_pool_init);
+
+/**
+ * octeon_fpa3_release_pool() - Release a pool.
+ * @node: Node pool is on.
+ * @pool: Pool to release.
+ */
+void octeon_fpa3_release_pool(int node, int pool)
+{
+ struct global_resource_tag tag;
+ char buf[16];
+
+ mutex_lock(&octeon_fpa3_lock);
+
+ strncpy((char *)&tag.lo, "cvm_pool", 8);
+ snprintf(buf, 16, "_%d......", node);
+ memcpy(&tag.hi, buf, 8);
+
+ res_mgr_free(tag, pool);
+
+ mutex_unlock(&octeon_fpa3_lock);
+}
+EXPORT_SYMBOL(octeon_fpa3_release_pool);
+
+/**
+ * octeon_fpa3_aura_init() - Initialize an aura.
+ * @node: Node to initialize aura on.
+ * @pool: Pool the aura belongs to.
+ * @aura_num: Requested aura number (-1 for don't care).
+ * @aura: Updated with the initialized aura number.
+ * @num_bufs: Number of buffers in the aura.
+ * @limit: Limit for the aura.
+ *
+ * Return: 0 if successful.
+ * < 0 for error codes.
+ */
+int octeon_fpa3_aura_init(int node, int pool, int aura_num,
+ int *aura, int num_bufs, unsigned int limit)
+{
+ struct global_resource_tag tag;
+ char buf[16];
+ u64 data, shift;
+ unsigned int drop, pass;
+ int rc = 0;
+
+ mutex_lock(&octeon_fpa3_lock);
+
+ strncpy((char *)&tag.lo, "cvm_aura", 8);
+ snprintf(buf, 16, "_%d......", node);
+ memcpy(&tag.hi, buf, 8);
+
+ res_mgr_create_resource(tag, get_num_auras());
+ *aura = res_mgr_alloc(tag, aura_num, true);
+ if (*aura < 0) {
+ rc = -ENODEV;
+ goto error;
+ }
+
+ oct_csr_write(0, FPA_AURAX_CFG(node, *aura));
+
+ /* Allow twice the limit before saturation at zero */
+ limit *= 2;
+ data = limit;
+ oct_csr_write(data, FPA_AURAX_CNT_LIMIT(node, *aura));
+ oct_csr_write(data, FPA_AURAX_CNT(node, *aura));
+
+ oct_csr_write(pool, FPA_AURAX_POOL(node, *aura));
+
+ /* No per-pool RED/Drop */
+ oct_csr_write(0, FPA_AURAX_POOL_LEVELS(node, *aura));
+
+ shift = 0;
+ while ((limit >> shift) > 255)
+ shift++;
+
+ drop = (limit - num_bufs / 20) >> shift; /* 95% */
+ pass = (limit - (num_bufs * 3) / 20) >> shift; /* 85% */
+
+ /* Enable per aura RED/drop */
+ data = BIT(38) | (shift << 32) | (drop << 16) | (pass << 8);
+ oct_csr_write(data, FPA_AURAX_CNT_LEVELS(node, *aura));
+
+error:
+ mutex_unlock(&octeon_fpa3_lock);
+ return rc;
+}
+EXPORT_SYMBOL(octeon_fpa3_aura_init);
+
+/**
+ * octeon_fpa3_release_aura() - Release an aura.
+ * @node: Node to aura is on.
+ * @aura: Aura to release.
+ */
+void octeon_fpa3_release_aura(int node, int aura)
+{
+ struct global_resource_tag tag;
+ char buf[16];
+
+ mutex_lock(&octeon_fpa3_lock);
+
+ strncpy((char *)&tag.lo, "cvm_aura", 8);
+ snprintf(buf, 16, "_%d......", node);
+ memcpy(&tag.hi, buf, 8);
+
+ res_mgr_free(tag, aura);
+
+ mutex_unlock(&octeon_fpa3_lock);
+}
+EXPORT_SYMBOL(octeon_fpa3_release_aura);
+
+/**
+ * octeon_fpa3_alloc() - Get a buffer from a aura's pool.
+ * @node: Node to free memory to.
+ * @aura: Aura to free memory to.
+ *
+ * Return: Allocated buffer pointer if successful, NULL on error.
+ */
+void *octeon_fpa3_alloc(u64 node, int aura)
+{
+ u64 buf_phys, addr;
+ void *buf = NULL;
+
+ /* Buffer pointers are obtained using load operations */
+ addr = BIT(63) | BIT(48) | (0x29ull << 40) | (node << 36) |
+ (aura << 16);
+ buf_phys = *(u64 *)addr;
+
+ if (buf_phys)
+ buf = phys_to_virt(buf_phys);
+
+ return buf;
+}
+EXPORT_SYMBOL(octeon_fpa3_alloc);
+
+/**
+ * octeon_fpa3_free() - Add a buffer back to the aura's pool.
+ * @node: Node to free memory to.
+ * @aura: Aura to free memory to.
+ * @buf: Address of buffer to free to the aura's pool.
+ */
+void octeon_fpa3_free(u64 node, int aura, const void *buf)
+{
+ u64 buf_phys, addr;
+
+ buf_phys = virt_to_phys(buf);
+
+ /* Make sure that any previous writes to memory go out before we free
+ * this buffer. This also serves as a barrier to prevent GCC from
+ * reordering operations to after the free.
+ */
+ wmb();
+
+ /* Buffers are added to fpa pools using store operations */
+ addr = BIT(63) | BIT(48) | (0x29ull << 40) | (node << 36);
+ addr |= (aura << 16);
+ *(u64 *)addr = buf_phys;
+}
+EXPORT_SYMBOL(octeon_fpa3_free);
+
+/**
+ * octeon_fpa3_mem_fill() - Add buffers to an aura.
+ * @node: Node to get memory from.
+ * @cache: Memory cache to allocate from.
+ * @aura: Aura to add buffers to.
+ * @num_bufs: Number of buffers to add to the aura.
+ *
+ * Return: 0 if successful.
+ * < 0 for error codes.
+ */
+int octeon_fpa3_mem_fill(int node, struct kmem_cache *cache,
+ int aura, int num_bufs)
+{
+ void *mem;
+ int i, rc = 0;
+
+ mutex_lock(&octeon_fpa3_lock);
+
+ for (i = 0; i < num_bufs; i++) {
+ mem = kmem_cache_alloc_node(cache, GFP_KERNEL, node);
+ if (!mem) {
+ pr_err("Failed to allocate memory for aura=%d\n", aura);
+ rc = -ENOMEM;
+ break;
+ }
+ octeon_fpa3_free(node, aura, mem);
+ }
+
+ mutex_unlock(&octeon_fpa3_lock);
+ return rc;
+}
+EXPORT_SYMBOL(octeon_fpa3_mem_fill);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Cavium, Inc. Octeon III FPA manager.");
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 0411efdb465c..f36263c46e60 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -10,6 +10,7 @@
#include <asm/octeon/cvmx.h>
#include <asm/bitfield.h>
+#include <linux/slab.h>
extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
uint64_t alignment,
@@ -364,6 +365,18 @@ int res_mgr_alloc_range(struct global_resource_tag tag, int req_inst,
int req_cnt, bool use_last_avail, int *inst);
int res_mgr_create_resource(struct global_resource_tag tag, int inst_cnt);
+int octeon_fpa3_init(int node);
+int octeon_fpa3_pool_init(int node, int pool_num, int *pool, void **pool_stack,
+ int num_ptrs);
+int octeon_fpa3_aura_init(int node, int pool, int aura_num, int *aura,
+ int num_bufs, unsigned int limit);
+int octeon_fpa3_mem_fill(int node, struct kmem_cache *cache, int aura,
+ int num_bufs);
+void octeon_fpa3_free(u64 node, int aura, const void *buf);
+void *octeon_fpa3_alloc(u64 node, int aura);
+void octeon_fpa3_release_pool(int node, int pool);
+void octeon_fpa3_release_aura(int node, int aura);
+
/**
* Read a 32bit value from the Octeon NPI register space
*
--
2.14.3
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