| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <1514395808-16916-3-git-send-email-Tomer.Tayar@cavium.com>
Date: Wed, 27 Dec 2017 19:30:06 +0200
From: Tomer Tayar <Tomer.Tayar@...ium.com>
To: <davem@...emloft.net>, <netdev@...r.kernel.org>
CC: <linux-rdma@...r.kernel.org>, <linux-scsi@...r.kernel.org>,
Tomer Tayar <Tomer.Tayar@...ium.com>,
Ariel Elior <Ariel.Elior@...ium.com>,
"Michal Kalderon" <Michal.Kalderon@...ium.com>,
Chad Dupuis <Chad.Dupuis@...ium.com>,
Manish Rangankar <Manish.Rangankar@...ium.com>
Subject: [PATCH v4 net-next 2/4] qed*: HSI renaming for different types of HW
This patch renames defines and structures in the FW HSI files to allow a
distinction between different types of HW.
Signed-off-by: Ariel Elior <Ariel.Elior@...ium.com>
Signed-off-by: Michal Kalderon <Michal.Kalderon@...ium.com>
Signed-off-by: Chad Dupuis <Chad.Dupuis@...ium.com>
Signed-off-by: Manish Rangankar <Manish.Rangankar@...ium.com>
Signed-off-by: Tomer Tayar <Tomer.Tayar@...ium.com>
---
drivers/infiniband/hw/qedr/main.c | 2 +-
drivers/net/ethernet/qlogic/qed/qed_cxt.c | 16 +-
drivers/net/ethernet/qlogic/qed/qed_debug.c | 112 +-
drivers/net/ethernet/qlogic/qed/qed_fcoe.c | 10 +-
drivers/net/ethernet/qlogic/qed/qed_hsi.h | 7570 ++++++++++----------
.../net/ethernet/qlogic/qed/qed_init_fw_funcs.c | 33 +-
drivers/net/ethernet/qlogic/qed/qed_int.c | 4 +-
drivers/net/ethernet/qlogic/qed/qed_int.h | 2 +-
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h | 138 +-
drivers/net/ethernet/qlogic/qed/qed_spq.c | 8 +-
drivers/net/ethernet/qlogic/qed/qed_sriov.c | 10 +-
drivers/net/ethernet/qlogic/qede/qede_main.c | 2 +-
drivers/scsi/qedf/drv_fcoe_fw_funcs.c | 8 +-
drivers/scsi/qedf/drv_fcoe_fw_funcs.h | 2 +-
drivers/scsi/qedf/qedf.h | 4 +-
drivers/scsi/qedf/qedf_els.c | 2 +-
drivers/scsi/qedf/qedf_io.c | 16 +-
drivers/scsi/qedf/qedf_main.c | 8 +-
drivers/scsi/qedi/qedi_debugfs.c | 4 +-
drivers/scsi/qedi/qedi_fw.c | 46 +-
drivers/scsi/qedi/qedi_fw_api.c | 27 +-
drivers/scsi/qedi/qedi_fw_iscsi.h | 2 +-
drivers/scsi/qedi/qedi_iscsi.h | 2 +-
drivers/scsi/qedi/qedi_main.c | 8 +-
include/linux/qed/common_hsi.h | 30 +-
include/linux/qed/fcoe_common.h | 362 +-
include/linux/qed/iscsi_common.h | 360 +-
include/linux/qed/qed_if.h | 4 +-
28 files changed, 4399 insertions(+), 4393 deletions(-)
diff --git a/drivers/infiniband/hw/qedr/main.c b/drivers/infiniband/hw/qedr/main.c
index 50812b3..a9c3378 100644
--- a/drivers/infiniband/hw/qedr/main.c
+++ b/drivers/infiniband/hw/qedr/main.c
@@ -264,7 +264,7 @@ static int qedr_register_device(struct qedr_dev *dev)
static int qedr_alloc_mem_sb(struct qedr_dev *dev,
struct qed_sb_info *sb_info, u16 sb_id)
{
- struct status_block *sb_virt;
+ struct status_block_e4 *sb_virt;
dma_addr_t sb_phys;
int rc;
diff --git a/drivers/net/ethernet/qlogic/qed/qed_cxt.c b/drivers/net/ethernet/qlogic/qed/qed_cxt.c
index 043f2cb..aa95d88 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_cxt.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_cxt.c
@@ -86,22 +86,22 @@
/* connection context union */
union conn_context {
- struct core_conn_context core_ctx;
- struct eth_conn_context eth_ctx;
- struct iscsi_conn_context iscsi_ctx;
- struct fcoe_conn_context fcoe_ctx;
- struct roce_conn_context roce_ctx;
+ struct e4_core_conn_context core_ctx;
+ struct e4_eth_conn_context eth_ctx;
+ struct e4_iscsi_conn_context iscsi_ctx;
+ struct e4_fcoe_conn_context fcoe_ctx;
+ struct e4_roce_conn_context roce_ctx;
};
/* TYPE-0 task context - iSCSI, FCOE */
union type0_task_context {
- struct iscsi_task_context iscsi_ctx;
- struct fcoe_task_context fcoe_ctx;
+ struct e4_iscsi_task_context iscsi_ctx;
+ struct e4_fcoe_task_context fcoe_ctx;
};
/* TYPE-1 task context - ROCE */
union type1_task_context {
- struct rdma_task_context roce_ctx;
+ struct e4_rdma_task_context roce_ctx;
};
struct src_ent {
diff --git a/drivers/net/ethernet/qlogic/qed/qed_debug.c b/drivers/net/ethernet/qlogic/qed/qed_debug.c
index 0fbeaf9..847b6f8 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_debug.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_debug.c
@@ -610,9 +610,9 @@ struct dbg_array {
"cnig",
{false, true}, false, 0,
{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},
- CNIG_REG_DBG_SELECT_K2, CNIG_REG_DBG_DWORD_ENABLE_K2,
- CNIG_REG_DBG_SHIFT_K2, CNIG_REG_DBG_FORCE_VALID_K2,
- CNIG_REG_DBG_FORCE_FRAME_K2,
+ CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5,
+ CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5,
+ CNIG_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 0
};
@@ -654,11 +654,11 @@ struct dbg_array {
"pcie",
{false, true}, false, 0,
{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
- PCIE_REG_DBG_COMMON_SELECT_K2,
- PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2,
- PCIE_REG_DBG_COMMON_SHIFT_K2,
- PCIE_REG_DBG_COMMON_FORCE_VALID_K2,
- PCIE_REG_DBG_COMMON_FORCE_FRAME_K2,
+ PCIE_REG_DBG_COMMON_SELECT_K2_E5,
+ PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
+ PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
+ PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
+ PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
false, false, MAX_DBG_RESET_REGS, 0
};
@@ -760,9 +760,9 @@ struct dbg_array {
"pglcs",
{false, true}, false, 0,
{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
- PGLCS_REG_DBG_SELECT_K2, PGLCS_REG_DBG_DWORD_ENABLE_K2,
- PGLCS_REG_DBG_SHIFT_K2, PGLCS_REG_DBG_FORCE_VALID_K2,
- PGLCS_REG_DBG_FORCE_FRAME_K2,
+ PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5,
+ PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5,
+ PGLCS_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 2
};
@@ -1255,9 +1255,9 @@ struct dbg_array {
"umac",
{false, true}, false, 0,
{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},
- UMAC_REG_DBG_SELECT_K2, UMAC_REG_DBG_DWORD_ENABLE_K2,
- UMAC_REG_DBG_SHIFT_K2, UMAC_REG_DBG_FORCE_VALID_K2,
- UMAC_REG_DBG_FORCE_FRAME_K2,
+ UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5,
+ UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5,
+ UMAC_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 6
};
@@ -1289,9 +1289,9 @@ struct dbg_array {
"wol",
{false, true}, false, 0,
{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},
- WOL_REG_DBG_SELECT_K2, WOL_REG_DBG_DWORD_ENABLE_K2,
- WOL_REG_DBG_SHIFT_K2, WOL_REG_DBG_FORCE_VALID_K2,
- WOL_REG_DBG_FORCE_FRAME_K2,
+ WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5,
+ WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5,
+ WOL_REG_DBG_FORCE_FRAME_K2_E5,
true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7
};
@@ -1299,9 +1299,9 @@ struct dbg_array {
"bmbn",
{false, true}, false, 0,
{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB},
- BMBN_REG_DBG_SELECT_K2, BMBN_REG_DBG_DWORD_ENABLE_K2,
- BMBN_REG_DBG_SHIFT_K2, BMBN_REG_DBG_FORCE_VALID_K2,
- BMBN_REG_DBG_FORCE_FRAME_K2,
+ BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5,
+ BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5,
+ BMBN_REG_DBG_FORCE_FRAME_K2_E5,
false, false, MAX_DBG_RESET_REGS, 0
};
@@ -1316,9 +1316,9 @@ struct dbg_array {
"nwm",
{false, true}, false, 0,
{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},
- NWM_REG_DBG_SELECT_K2, NWM_REG_DBG_DWORD_ENABLE_K2,
- NWM_REG_DBG_SHIFT_K2, NWM_REG_DBG_FORCE_VALID_K2,
- NWM_REG_DBG_FORCE_FRAME_K2,
+ NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5,
+ NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5,
+ NWM_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0
};
@@ -1326,9 +1326,9 @@ struct dbg_array {
"nws",
{false, true}, false, 0,
{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},
- NWS_REG_DBG_SELECT_K2, NWS_REG_DBG_DWORD_ENABLE_K2,
- NWS_REG_DBG_SHIFT_K2, NWS_REG_DBG_FORCE_VALID_K2,
- NWS_REG_DBG_FORCE_FRAME_K2,
+ NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5,
+ NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5,
+ NWS_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 12
};
@@ -1336,9 +1336,9 @@ struct dbg_array {
"ms",
{false, true}, false, 0,
{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},
- MS_REG_DBG_SELECT_K2, MS_REG_DBG_DWORD_ENABLE_K2,
- MS_REG_DBG_SHIFT_K2, MS_REG_DBG_FORCE_VALID_K2,
- MS_REG_DBG_FORCE_FRAME_K2,
+ MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5,
+ MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5,
+ MS_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 13
};
@@ -1346,11 +1346,11 @@ struct dbg_array {
"phy_pcie",
{false, true}, false, 0,
{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
- PCIE_REG_DBG_COMMON_SELECT_K2,
- PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2,
- PCIE_REG_DBG_COMMON_SHIFT_K2,
- PCIE_REG_DBG_COMMON_FORCE_VALID_K2,
- PCIE_REG_DBG_COMMON_FORCE_FRAME_K2,
+ PCIE_REG_DBG_COMMON_SELECT_K2_E5,
+ PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
+ PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
+ PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
+ PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
false, false, MAX_DBG_RESET_REGS, 0
};
@@ -1659,7 +1659,7 @@ struct dbg_array {
{true, true} },
/* DBG_RESET_REG_MISCS_PL_HV_2 */
- { MISCS_REG_RESET_PL_HV_2_K2, 0x0,
+ { MISCS_REG_RESET_PL_HV_2_K2_E5, 0x0,
{false, true} },
/* DBG_RESET_REG_MISC_PL_UA */
@@ -1685,25 +1685,25 @@ struct dbg_array {
static struct phy_defs s_phy_defs[] = {
{"nw_phy", NWS_REG_NWS_CMU_K2,
- PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2,
- PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2,
- PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2,
- PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2},
- {"sgmii_phy", MS_REG_MS_CMU_K2,
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2,
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2,
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2,
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2},
- {"pcie_phy0", PHY_PCIE_REG_PHY0_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2},
- {"pcie_phy1", PHY_PCIE_REG_PHY1_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2},
+ PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5,
+ PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5,
+ PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5,
+ PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5},
+ {"sgmii_phy", MS_REG_MS_CMU_K2_E5,
+ PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
+ PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
+ PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
+ PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
+ {"pcie_phy0", PHY_PCIE_REG_PHY0_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
+ {"pcie_phy1", PHY_PCIE_REG_PHY1_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
};
/**************************** Private Functions ******************************/
@@ -1795,7 +1795,7 @@ static void qed_read_fw_info(struct qed_hwfn *p_hwfn,
* The address is located in the last line of the Storm RAM.
*/
addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM +
- DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE) -
+ DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE_BB_K2) -
sizeof(fw_info_location);
dest = (u32 *)&fw_info_location;
@@ -3637,7 +3637,7 @@ static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn,
dump,
NULL,
BYTES_TO_DWORDS(MCP_REG_SCRATCH),
- MCP_REG_SCRATCH_SIZE,
+ MCP_REG_SCRATCH_SIZE_BB_K2,
false, 0, false, "MCP", false, 0);
/* Dump MCP cpu_reg_file */
diff --git a/drivers/net/ethernet/qlogic/qed/qed_fcoe.c b/drivers/net/ethernet/qlogic/qed/qed_fcoe.c
index df195c0..2dc9b31 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_fcoe.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_fcoe.c
@@ -115,7 +115,7 @@ struct qed_fcoe_conn {
struct qed_fcoe_pf_params *fcoe_pf_params = NULL;
struct fcoe_init_ramrod_params *p_ramrod = NULL;
struct fcoe_init_func_ramrod_data *p_data;
- struct fcoe_conn_context *p_cxt = NULL;
+ struct e4_fcoe_conn_context *p_cxt = NULL;
struct qed_spq_entry *p_ent = NULL;
struct qed_sp_init_data init_data;
struct qed_cxt_info cxt_info;
@@ -167,7 +167,7 @@ struct qed_fcoe_conn {
}
p_cxt = cxt_info.p_cxt;
SET_FIELD(p_cxt->tstorm_ag_context.flags3,
- TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN, 1);
+ E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN, 1);
fcoe_pf_params->dummy_icid = (u16)dummy_cid;
@@ -568,7 +568,7 @@ int qed_fcoe_alloc(struct qed_hwfn *p_hwfn)
void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
{
- struct fcoe_task_context *p_task_ctx = NULL;
+ struct e4_fcoe_task_context *p_task_ctx = NULL;
int rc;
u32 i;
@@ -580,13 +580,13 @@ void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
if (rc)
continue;
- memset(p_task_ctx, 0, sizeof(struct fcoe_task_context));
+ memset(p_task_ctx, 0, sizeof(struct e4_fcoe_task_context));
SET_FIELD(p_task_ctx->timer_context.logical_client_0,
TIMERS_CONTEXT_VALIDLC0, 1);
SET_FIELD(p_task_ctx->timer_context.logical_client_1,
TIMERS_CONTEXT_VALIDLC1, 1);
SET_FIELD(p_task_ctx->tstorm_ag_context.flags0,
- TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE, 1);
+ E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE, 1);
}
}
diff --git a/drivers/net/ethernet/qlogic/qed/qed_hsi.h b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
index 302a253..21760f4 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_hsi.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
@@ -382,216 +382,216 @@ struct xstorm_core_conn_st_ctx {
__le32 reserved0[55];
};
-struct xstorm_core_conn_ag_ctx {
+struct e4_xstorm_core_conn_ag_ctx {
u8 reserved0;
u8 core_state;
u8 flags0;
-#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
+#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
u8 flags2;
-#define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
-#define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
u8 flags7;
-#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
u8 flags11;
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 consolid_prod;
@@ -645,89 +645,89 @@ struct xstorm_core_conn_ag_ctx {
__le16 word15;
};
-struct tstorm_core_conn_ag_ctx {
+struct e4_tstorm_core_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
-#define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
-#define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
-#define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
-#define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
-#define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
u8 flags2;
-#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
-#define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
-#define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
-#define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
-#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
-#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
u8 flags4;
-#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
-#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
-#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
__le32 reg2;
@@ -749,63 +749,63 @@ struct tstorm_core_conn_ag_ctx {
__le32 reg10;
};
-struct ustorm_core_conn_ag_ctx {
+struct e4_ustorm_core_conn_ag_ctx {
u8 reserved;
u8 byte1;
u8 flags0;
-#define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
-#define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
-#define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
+#define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
+#define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
-#define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
-#define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
+#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
+#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
-#define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -829,15 +829,15 @@ struct ustorm_core_conn_st_ctx {
};
/* core connection context */
-struct core_conn_context {
+struct e4_core_conn_context {
struct ystorm_core_conn_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct pstorm_core_conn_st_ctx pstorm_st_context;
struct regpair pstorm_st_padding[2];
struct xstorm_core_conn_st_ctx xstorm_st_context;
- struct xstorm_core_conn_ag_ctx xstorm_ag_context;
- struct tstorm_core_conn_ag_ctx tstorm_ag_context;
- struct ustorm_core_conn_ag_ctx ustorm_ag_context;
+ struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
+ struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
+ struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
struct mstorm_core_conn_st_ctx mstorm_st_context;
struct ustorm_core_conn_st_ctx ustorm_st_context;
struct regpair ustorm_st_padding[2];
@@ -1402,74 +1402,74 @@ enum dmae_cmd_src_enum {
MAX_DMAE_CMD_SRC_ENUM
};
-struct mstorm_core_conn_ag_ctx {
+struct e4_mstorm_core_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
-struct ystorm_core_conn_ag_ctx {
+struct e4_ystorm_core_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -1620,22 +1620,22 @@ struct qm_rf_opportunistic_mask {
};
/* QM hardware structure of QM map memory */
-struct qm_rf_pq_map {
+struct qm_rf_pq_map_e4 {
__le32 reg;
-#define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1
-#define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
-#define QM_RF_PQ_MAP_RL_ID_MASK 0xFF
-#define QM_RF_PQ_MAP_RL_ID_SHIFT 1
-#define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
-#define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
-#define QM_RF_PQ_MAP_VOQ_MASK 0x1F
-#define QM_RF_PQ_MAP_VOQ_SHIFT 18
-#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
-#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
-#define QM_RF_PQ_MAP_RL_VALID_MASK 0x1
-#define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
-#define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
-#define QM_RF_PQ_MAP_RESERVED_SHIFT 26
+#define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1
+#define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0
+#define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF
+#define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1
+#define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF
+#define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9
+#define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F
+#define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18
+#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3
+#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23
+#define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1
+#define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25
+#define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F
+#define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26
};
/* Completion params for aggregated interrupt completion */
@@ -4608,219 +4608,219 @@ struct xstorm_eth_conn_st_ctx {
__le32 reserved[60];
};
-struct xstorm_eth_conn_ag_ctx {
+struct e4_xstorm_eth_conn_ag_ctx {
u8 reserved0;
u8 eth_state;
u8 flags0;
-#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
u8 flags2;
-#define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
-#define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
u8 flags7;
-#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
u8 flags10;
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
u8 flags11;
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
u8 edpm_event_id;
__le16 physical_q0;
- __le16 ereserved1;
+ __le16 e5_reserved1;
__le16 edpm_num_bds;
__le16 tx_bd_cons;
__le16 tx_bd_prod;
@@ -4853,7 +4853,7 @@ struct xstorm_eth_conn_ag_ctx {
u8 byte13;
u8 byte14;
u8 byte15;
- u8 ereserved;
+ u8 e5_reserved;
__le16 word11;
__le32 reg10;
__le32 reg11;
@@ -4876,37 +4876,37 @@ struct ystorm_eth_conn_st_ctx {
__le32 reserved[8];
};
-struct ystorm_eth_conn_ag_ctx {
+struct e4_ystorm_eth_conn_ag_ctx {
u8 byte0;
u8 state;
u8 flags0;
-#define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
-#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
-#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
-#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
-#define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
+#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
+#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
+#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
+#define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
-#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
-#define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
+#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
+#define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 tx_q0_int_coallecing_timeset;
u8 byte3;
__le16 word0;
@@ -4920,89 +4920,89 @@ struct ystorm_eth_conn_ag_ctx {
__le32 reg3;
};
-struct tstorm_eth_conn_ag_ctx {
+struct e4_tstorm_eth_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
u8 flags2;
-#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
-#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
-#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
u8 flags4;
-#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
-#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
-#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
-#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
__le32 reg2;
@@ -5024,63 +5024,63 @@ struct tstorm_eth_conn_ag_ctx {
__le32 reg10;
};
-struct ustorm_eth_conn_ag_ctx {
+struct e4_ustorm_eth_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
-#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
-#define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
+#define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
-#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
-#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
+#define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
u8 flags2;
-#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
-#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
-#define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
-#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
-#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
-#define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
+#define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
-#define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -5104,16 +5104,16 @@ struct mstorm_eth_conn_st_ctx {
};
/* eth connection context */
-struct eth_conn_context {
+struct e4_eth_conn_context {
struct tstorm_eth_conn_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2];
struct pstorm_eth_conn_st_ctx pstorm_st_context;
struct xstorm_eth_conn_st_ctx xstorm_st_context;
- struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
+ struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
struct ystorm_eth_conn_st_ctx ystorm_st_context;
- struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
- struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
- struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
+ struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
+ struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
+ struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
struct ustorm_eth_conn_st_ctx ustorm_st_context;
struct mstorm_eth_conn_st_ctx mstorm_st_context;
};
@@ -5661,219 +5661,219 @@ struct vport_update_ramrod_data {
struct eth_vport_rss_config rss_config;
};
-struct xstorm_eth_conn_agctxdq_ext_ldpart {
+struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart {
u8 reserved0;
u8 eth_state;
u8 flags0;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
u8 flags2;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
u8 flags3;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
u8 flags4;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
u8 flags5;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
u8 flags6;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
u8 flags7;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
u8 flags10;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
u8 flags11;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
u8 edpm_event_id;
__le16 physical_q0;
- __le16 ereserved1;
+ __le16 e5_reserved1;
__le16 edpm_num_bds;
__le16 tx_bd_cons;
__le16 tx_bd_prod;
@@ -5890,256 +5890,256 @@ struct xstorm_eth_conn_agctxdq_ext_ldpart {
__le32 reg4;
};
-struct mstorm_eth_conn_ag_ctx {
+struct e4_mstorm_eth_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
-struct xstorm_eth_hw_conn_ag_ctx {
+struct e4_xstorm_eth_hw_conn_ag_ctx {
u8 reserved0;
u8 eth_state;
u8 flags0;
-#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
u8 flags2;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
u8 flags7;
-#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
u8 flags10;
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
u8 flags11;
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
u8 edpm_event_id;
__le16 physical_q0;
- __le16 ereserved1;
+ __le16 e5_reserved1;
__le16 edpm_num_bds;
__le16 tx_bd_cons;
__le16 tx_bd_prod;
@@ -6354,49 +6354,49 @@ struct ystorm_rdma_task_st_ctx {
struct regpair temp[4];
};
-struct ystorm_rdma_task_ag_ctx {
+struct e4_ystorm_rdma_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 msem_ctx_upd_seq;
u8 flags0;
-#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
-#define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
-#define YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
-#define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
-#define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
-#define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
-#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
-#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
-#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
-#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
-#define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
-#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 key;
__le32 mw_cnt;
u8 ref_cnt_seq;
@@ -6410,49 +6410,49 @@ struct ystorm_rdma_task_ag_ctx {
__le32 fbo_hi;
};
-struct mstorm_rdma_task_ag_ctx {
+struct e4_mstorm_rdma_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
-#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
-#define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
-#define MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
-#define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
-#define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
-#define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
-#define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
-#define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
-#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
-#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
-#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
-#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 key;
__le32 mw_cnt;
u8 ref_cnt_seq;
@@ -6476,56 +6476,56 @@ struct ustorm_rdma_task_st_ctx {
struct regpair temp[2];
};
-struct ustorm_rdma_task_ag_ctx {
+struct e4_ustorm_rdma_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
-#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
-#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
+#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
u8 flags1;
-#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
-#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
-#define USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
-#define USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
+#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
u8 flags2;
-#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
-#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
-#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
-#define USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
-#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
-#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
-#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
+#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
+#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
u8 flags3;
-#define USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
-#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
-#define USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
-#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 reg2;
@@ -6535,16 +6535,16 @@ struct ustorm_rdma_task_ag_ctx {
};
/* RDMA task context */
-struct rdma_task_context {
+struct e4_rdma_task_context {
struct ystorm_rdma_task_st_ctx ystorm_st_context;
- struct ystorm_rdma_task_ag_ctx ystorm_ag_context;
+ struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context;
struct tdif_task_context tdif_context;
- struct mstorm_rdma_task_ag_ctx mstorm_ag_context;
+ struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context;
struct mstorm_rdma_task_st_ctx mstorm_st_context;
struct rdif_task_context rdif_context;
struct ustorm_rdma_task_st_ctx ustorm_st_context;
struct regpair ustorm_st_padding[2];
- struct ustorm_rdma_task_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context;
};
/* rdma function init ramrod data */
@@ -6771,214 +6771,214 @@ enum rdma_tid_type {
MAX_RDMA_TID_TYPE
};
-struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
+struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
u8 reserved0;
u8 state;
u8 flags0;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
u8 flags1;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
u8 flags2;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
u8 flags3;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
u8 flags4;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
u8 flags5;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
u8 flags6;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
u8 flags7;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
u8 flags11;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 word1;
@@ -6998,126 +6998,126 @@ struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
__le32 reg4;
};
-struct mstorm_rdma_conn_ag_ctx {
+struct e4_mstorm_rdma_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
-struct tstorm_rdma_conn_ag_ctx {
+struct e4_tstorm_rdma_conn_ag_ctx {
u8 reserved0;
u8 byte1;
u8 flags0;
-#define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags2;
-#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
-#define TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
-#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
u8 flags4;
-#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
-#define TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
-#define TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
__le32 reg2;
@@ -7139,73 +7139,73 @@ struct tstorm_rdma_conn_ag_ctx {
__le32 reg10;
};
-struct tstorm_rdma_task_ag_ctx {
+struct e4_tstorm_rdma_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
-#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
-#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
-#define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
-#define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
-#define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
-#define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
+#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
+#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
-#define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
-#define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
-#define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
-#define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
-#define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
-#define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
-#define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
-#define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
u8 flags3;
-#define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
-#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
-#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
-#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
-#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
-#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
-#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
u8 flags4;
-#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
-#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
-#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
-#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
-#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
-#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
-#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 byte2;
__le16 word1;
__le32 reg0;
@@ -7218,63 +7218,63 @@ struct tstorm_rdma_task_ag_ctx {
__le32 reg2;
};
-struct ustorm_rdma_conn_ag_ctx {
+struct e4_ustorm_rdma_conn_ag_ctx {
u8 reserved;
u8 byte1;
u8 flags0;
-#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
-#define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
-#define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
-#define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
-#define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
+#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
u8 flags3;
-#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
-#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 conn_dpi;
@@ -7287,214 +7287,214 @@ struct ustorm_rdma_conn_ag_ctx {
__le16 word3;
};
-struct xstorm_rdma_conn_ag_ctx {
+struct e4_xstorm_rdma_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
u8 flags1;
-#define XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
u8 flags2;
-#define XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags4;
-#define XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
u8 flags7;
-#define XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
u8 flags11;
-#define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 word1;
@@ -7516,37 +7516,37 @@ struct xstorm_rdma_conn_ag_ctx {
__le32 reg6;
};
-struct ystorm_rdma_conn_ag_ctx {
+struct e4_ystorm_rdma_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -7591,16 +7591,16 @@ struct ustorm_roce_conn_st_ctx {
};
/* roce connection context */
-struct roce_conn_context {
+struct e4_roce_conn_context {
struct ystorm_roce_conn_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct pstorm_roce_conn_st_ctx pstorm_st_context;
struct xstorm_roce_conn_st_ctx xstorm_st_context;
struct regpair xstorm_st_padding[2];
- struct xstorm_rdma_conn_ag_ctx xstorm_ag_context;
- struct tstorm_rdma_conn_ag_ctx tstorm_ag_context;
+ struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context;
+ struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context;
struct timers_context timer_context;
- struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
struct tstorm_roce_conn_st_ctx tstorm_st_context;
struct mstorm_roce_conn_st_ctx mstorm_st_context;
struct ustorm_roce_conn_st_ctx ustorm_st_context;
@@ -7892,163 +7892,163 @@ enum roce_ramrod_cmd_id {
MAX_ROCE_RAMROD_CMD_ID
};
-struct mstorm_roce_req_conn_ag_ctx {
+struct e4_mstorm_roce_req_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
-struct mstorm_roce_resp_conn_ag_ctx {
+struct e4_mstorm_roce_resp_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
-struct tstorm_roce_req_conn_ag_ctx {
+struct e4_tstorm_roce_req_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
u8 flags1;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags2;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
u8 flags3;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
u8 flags4;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 snd_nxt_psn;
__le32 snd_max_psn;
@@ -8070,89 +8070,89 @@ struct tstorm_roce_req_conn_ag_ctx {
__le32 reg10;
};
-struct tstorm_roce_resp_conn_ag_ctx {
+struct e4_tstorm_roce_resp_conn_ag_ctx {
u8 byte0;
u8 state;
u8 flags0;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags2;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
u8 flags4;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 psn_and_rxmit_id_echo;
__le32 reg1;
__le32 reg2;
@@ -8174,63 +8174,63 @@ struct tstorm_roce_resp_conn_ag_ctx {
__le32 reg10;
};
-struct ustorm_roce_req_conn_ag_ctx {
+struct e4_ustorm_roce_req_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -8243,63 +8243,63 @@ struct ustorm_roce_req_conn_ag_ctx {
__le16 word3;
};
-struct ustorm_roce_resp_conn_ag_ctx {
+struct e4_ustorm_roce_resp_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -8312,214 +8312,214 @@ struct ustorm_roce_resp_conn_ag_ctx {
__le16 word3;
};
-struct xstorm_roce_req_conn_ag_ctx {
+struct e4_xstorm_roce_req_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
u8 flags2;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags4;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
u8 flags7;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
u8 flags11;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
u8 flags13;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 word1;
@@ -8541,223 +8541,223 @@ struct xstorm_roce_req_conn_ag_ctx {
__le32 orq_cons;
};
-struct xstorm_roce_resp_conn_ag_ctx {
+struct e4_xstorm_roce_resp_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
u8 flags2;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags4;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
u8 flags7;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
u8 flags11;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 word1;
__le16 irq_prod;
__le16 word3;
__le16 word4;
- __le16 ereserved1;
+ __le16 e5_reserved1;
__le16 irq_cons;
u8 rxmit_opcode;
u8 byte4;
@@ -8772,37 +8772,37 @@ struct xstorm_roce_resp_conn_ag_ctx {
__le32 msn_and_syndrome;
};
-struct ystorm_roce_req_conn_ag_ctx {
+struct e4_ystorm_roce_req_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -8816,37 +8816,37 @@ struct ystorm_roce_req_conn_ag_ctx {
__le32 reg3;
};
-struct ystorm_roce_resp_conn_ag_ctx {
+struct e4_ystorm_roce_resp_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -8883,216 +8883,216 @@ struct xstorm_iwarp_conn_st_ctx {
__le32 reserved[44];
};
-struct xstorm_iwarp_conn_ag_ctx {
+struct e4_xstorm_iwarp_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
u8 flags1;
-#define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
u8 flags2;
-#define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
u8 flags3;
-#define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
-#define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
u8 flags7;
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
u8 flags11;
-#define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 physical_q1;
@@ -9140,89 +9140,89 @@ struct xstorm_iwarp_conn_ag_ctx {
__le32 reg17;
};
-struct tstorm_iwarp_conn_ag_ctx {
+struct e4_tstorm_iwarp_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3
-#define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
-#define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
u8 flags2;
-#define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
-#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6
-#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
u8 flags4;
-#define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
-#define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
-#define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
-#define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
__le32 unaligned_nxt_seq;
@@ -9260,17 +9260,17 @@ struct ustorm_iwarp_conn_st_ctx {
};
/* iwarp connection context */
-struct iwarp_conn_context {
+struct e4_iwarp_conn_context {
struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
struct regpair pstorm_st_padding[2];
struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
struct regpair xstorm_st_padding[2];
- struct xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
- struct tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
+ struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
+ struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
struct timers_context timer_context;
- struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2];
struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
@@ -9547,100 +9547,100 @@ struct unaligned_opaque_data {
__le32 cid;
};
-struct mstorm_iwarp_conn_ag_ctx {
+struct e4_mstorm_iwarp_conn_ag_ctx {
u8 reserved;
u8 state;
u8 flags0;
-#define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
-#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
-#define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
+#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
-#define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
-#define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 rcq_cons;
__le16 rcq_cons_th;
__le32 reg0;
__le32 reg1;
};
-struct ustorm_iwarp_conn_ag_ctx {
+struct e4_ustorm_iwarp_conn_ag_ctx {
u8 reserved;
u8 byte1;
u8 flags0;
-#define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
-#define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
-#define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
u8 flags3;
-#define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
-#define USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -9653,37 +9653,37 @@ struct ustorm_iwarp_conn_ag_ctx {
__le16 word3;
};
-struct ystorm_iwarp_conn_ag_ctx {
+struct e4_ystorm_iwarp_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -9871,216 +9871,216 @@ struct xstorm_fcoe_conn_st_ctx {
struct fcoe_wqe cached_wqes[16];
};
-struct xstorm_fcoe_conn_ag_ctx {
+struct e4_xstorm_fcoe_conn_ag_ctx {
u8 reserved0;
u8 fcoe_state;
u8 flags0;
-#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
u8 flags2;
-#define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
-#define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
u8 flags7;
-#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
u8 flags11;
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
u8 flags12;
-#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 word1;
@@ -10118,150 +10118,150 @@ struct ustorm_fcoe_conn_st_ctx {
u8 reserved[2];
};
-struct tstorm_fcoe_conn_ag_ctx {
+struct e4_tstorm_fcoe_conn_ag_ctx {
u8 reserved0;
u8 fcoe_state;
u8 flags0;
-#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
u8 flags1;
-#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
u8 flags2;
-#define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
-#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
-#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
u8 flags4;
-#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
-#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
-#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
};
-struct ustorm_fcoe_conn_ag_ctx {
+struct e4_ustorm_fcoe_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
-#define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
-#define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
-#define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
-#define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
-#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -10301,37 +10301,37 @@ struct tstorm_fcoe_conn_st_ctx {
u8 reserved0[5];
};
-struct mstorm_fcoe_conn_ag_ctx {
+struct e4_mstorm_fcoe_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
@@ -10376,21 +10376,21 @@ struct mstorm_fcoe_conn_st_ctx {
};
/* fcoe connection context */
-struct fcoe_conn_context {
+struct e4_fcoe_conn_context {
struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
struct regpair pstorm_st_padding[2];
struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
- struct xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
+ struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
struct regpair xstorm_ag_padding[6];
struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
struct regpair ustorm_st_padding[2];
- struct tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
+ struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
struct regpair tstorm_ag_padding[2];
struct timers_context timer_context;
- struct ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
- struct mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
+ struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
};
@@ -10441,37 +10441,37 @@ struct fcoe_stat_ramrod_params {
struct fcoe_stat_ramrod_data stat_ramrod_data;
};
-struct ystorm_fcoe_conn_ag_ctx {
+struct e4_ystorm_fcoe_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -10502,216 +10502,216 @@ struct xstorm_iscsi_tcp_conn_st_ctx {
__le32 reserved_tcp[4];
};
-struct xstorm_iscsi_conn_ag_ctx {
+struct e4_xstorm_iscsi_conn_ag_ctx {
u8 cdu_validation;
u8 state;
u8 flags0;
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
u8 flags1;
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
u8 flags2;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
u8 flags3;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
u8 flags6;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
u8 flags7;
-#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
u8 flags11;
-#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 physical_q1;
@@ -10747,7 +10747,7 @@ struct xstorm_iscsi_conn_ag_ctx {
u8 byte13;
u8 byte14;
u8 byte15;
- u8 ereserved;
+ u8 e5_reserved;
__le16 word11;
__le32 reg10;
__le32 reg11;
@@ -10759,89 +10759,89 @@ struct xstorm_iscsi_conn_ag_ctx {
__le32 reg17;
};
-struct tstorm_iscsi_conn_ag_ctx {
+struct e4_tstorm_iscsi_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
u8 flags2;
-#define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
-#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
-#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
u8 flags4;
-#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
-#define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
__le32 reg2;
@@ -10856,63 +10856,63 @@ struct tstorm_iscsi_conn_ag_ctx {
__le16 word0;
};
-struct ustorm_iscsi_conn_ag_ctx {
+struct e4_ustorm_iscsi_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
-#define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
-#define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
-#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
-#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
-#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -10930,37 +10930,37 @@ struct tstorm_iscsi_conn_st_ctx {
__le32 reserved[40];
};
-struct mstorm_iscsi_conn_ag_ctx {
+struct e4_mstorm_iscsi_conn_ag_ctx {
u8 reserved;
u8 state;
u8 flags0;
-#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
@@ -10979,7 +10979,7 @@ struct ustorm_iscsi_conn_st_ctx {
};
/* iscsi connection context */
-struct iscsi_conn_context {
+struct e4_iscsi_conn_context {
struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
@@ -10987,15 +10987,15 @@ struct iscsi_conn_context {
struct pb_context xpb2_context;
struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
struct regpair xstorm_st_padding[2];
- struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
- struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
+ struct e4_xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
+ struct e4_tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
struct regpair tstorm_ag_padding[2];
struct timers_context timer_context;
- struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
struct pb_context upb_context;
struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2];
- struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
+ struct e4_mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
};
@@ -11006,37 +11006,37 @@ struct iscsi_init_ramrod_params {
struct tcp_init_params tcp_init;
};
-struct ystorm_iscsi_conn_ag_ctx {
+struct e4_ystorm_iscsi_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
diff --git a/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c b/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
index e106e1b..8413615 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
@@ -64,7 +64,7 @@
#define QM_WFQ_VP_PQ_VOQ_SHIFT 0
/* Bit of PF in WFQ VP PQ map */
-#define QM_WFQ_VP_PQ_PF_SHIFT 5
+#define QM_WFQ_VP_PQ_PF_E4_SHIFT 5
/* 0x9000 = 4*9*1024 */
#define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
@@ -171,7 +171,7 @@ static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
if (pf_rl_en) {
/* Enable RLs for all VOQs */
STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_RT_OFFSET,
- (1 << MAX_NUM_VOQS) - 1);
+ (1 << MAX_NUM_VOQS_E4) - 1);
/* Write RL period */
STORE_RT_REG(p_hwfn,
QM_REG_RLPFPERIOD_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
@@ -260,7 +260,7 @@ static void qed_cmdq_lines_rt_init(
u8 tc, voq, port_id, num_tcs_in_port;
/* Clear PBF lines for all VOQs */
- for (voq = 0; voq < MAX_NUM_VOQS; voq++)
+ for (voq = 0; voq < MAX_NUM_VOQS_E4; voq++)
STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), 0);
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
if (port_params[port_id].active) {
@@ -387,7 +387,7 @@ static void qed_tx_pq_map_rt_init(
u8 voq = VOQ(p_params->port_id, p_params->pq_params[i].tc_id,
p_params->max_phys_tcs_per_port);
bool is_vf_pq = (i >= p_params->num_pf_pqs);
- struct qm_rf_pq_map tx_pq_map;
+ struct qm_rf_pq_map_e4 tx_pq_map;
bool rl_valid = p_params->pq_params[i].rl_valid &&
(p_params->pq_params[i].vport_id <
@@ -410,7 +410,7 @@ static void qed_tx_pq_map_rt_init(
first_tx_pq_id,
(voq << QM_WFQ_VP_PQ_VOQ_SHIFT) |
(p_params->pf_id <<
- QM_WFQ_VP_PQ_PF_SHIFT));
+ QM_WFQ_VP_PQ_PF_E4_SHIFT));
}
if (p_params->pq_params[i].rl_valid && !rl_valid)
@@ -418,15 +418,16 @@ static void qed_tx_pq_map_rt_init(
"Invalid VPORT ID for rate limiter configuration");
/* Fill PQ map entry */
memset(&tx_pq_map, 0, sizeof(tx_pq_map));
- SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_PQ_VALID, 1);
+ SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_E4_PQ_VALID, 1);
SET_FIELD(tx_pq_map.reg,
- QM_RF_PQ_MAP_RL_VALID, rl_valid ? 1 : 0);
- SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VP_PQ_ID, first_tx_pq_id);
- SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_ID,
+ QM_RF_PQ_MAP_E4_RL_VALID, rl_valid ? 1 : 0);
+ SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_E4_VP_PQ_ID,
+ first_tx_pq_id);
+ SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_E4_RL_ID,
rl_valid ?
p_params->pq_params[i].vport_id : 0);
- SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VOQ, voq);
- SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP,
+ SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_E4_VOQ, voq);
+ SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP,
p_params->pq_params[i].wrr_group);
/* Write PQ map entry to CAM */
STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id,
@@ -902,7 +903,7 @@ void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
if (reg_val)
- qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
+ qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
PRS_ETH_TUNN_FIC_FORMAT);
reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
@@ -929,7 +930,7 @@ void qed_set_gre_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
qed_set_tunnel_type_enable_bit(®_val, shift, ip_gre_enable);
qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
if (reg_val)
- qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
+ qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
PRS_ETH_TUNN_FIC_FORMAT);
reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
@@ -970,7 +971,7 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
if (reg_val)
- qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
+ qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
PRS_ETH_TUNN_FIC_FORMAT);
qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_ETH_ENABLE,
@@ -981,9 +982,9 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
if (QED_IS_BB_B0(p_hwfn->cdev))
return;
- qed_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN,
+ qed_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5,
eth_geneve_enable ? 1 : 0);
- qed_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN,
+ qed_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5,
ip_geneve_enable ? 1 : 0);
}
diff --git a/drivers/net/ethernet/qlogic/qed/qed_int.c b/drivers/net/ethernet/qlogic/qed/qed_int.c
index 8b2d141..d3eabcf 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_int.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_int.c
@@ -62,7 +62,7 @@ struct qed_sb_sp_info {
struct qed_sb_info sb_info;
/* per protocol index data */
- struct qed_pi_info pi_info_arr[PIS_PER_SB];
+ struct qed_pi_info pi_info_arr[PIS_PER_SB_E4];
};
enum qed_attention_type {
@@ -1313,7 +1313,7 @@ static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
if (IS_VF(p_hwfn->cdev))
return;
- sb_offset = igu_sb_id * PIS_PER_SB;
+ sb_offset = igu_sb_id * PIS_PER_SB_E4;
memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
diff --git a/drivers/net/ethernet/qlogic/qed/qed_int.h b/drivers/net/ethernet/qlogic/qed/qed_int.h
index 5199634..54b4ee0 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_int.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_int.h
@@ -197,7 +197,7 @@ void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
#define QED_SB_EVENT_MASK 0x0003
#define SB_ALIGNED_SIZE(p_hwfn) \
- ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
+ ALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn)
#define QED_SB_INVALID_IDX 0xffff
diff --git a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
index 0cdb433..0e5de76 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
@@ -564,7 +564,7 @@
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
#define PRS_REG_GRE_PROTOCOL 0x1f0734UL
#define PRS_REG_VXLAN_PORT 0x1f0738UL
-#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
+#define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL
#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
@@ -580,11 +580,11 @@
#define PRS_REG_NGE_PORT 0x1f086cUL
#define NIG_REG_NGE_PORT 0x508b38UL
-#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
-#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
-#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
-#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
-#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
+#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
+#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
+#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
+#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL
+#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL
#define NIG_REG_NGE_IP_ENABLE 0x508b28UL
#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
@@ -595,15 +595,15 @@
#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
#define QM_REG_WFQVPWEIGHT 0x2fa000UL
-#define PGLCS_REG_DBG_SELECT_K2 \
+#define PGLCS_REG_DBG_SELECT_K2_E5 \
0x001d14UL
-#define PGLCS_REG_DBG_DWORD_ENABLE_K2 \
+#define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \
0x001d18UL
-#define PGLCS_REG_DBG_SHIFT_K2 \
+#define PGLCS_REG_DBG_SHIFT_K2_E5 \
0x001d1cUL
-#define PGLCS_REG_DBG_FORCE_VALID_K2 \
+#define PGLCS_REG_DBG_FORCE_VALID_K2_E5 \
0x001d20UL
-#define PGLCS_REG_DBG_FORCE_FRAME_K2 \
+#define PGLCS_REG_DBG_FORCE_FRAME_K2_E5 \
0x001d24UL
#define MISC_REG_RESET_PL_PDA_VMAIN_1 \
0x008070UL
@@ -615,7 +615,7 @@
0x009050UL
#define MISCS_REG_RESET_PL_HV \
0x009060UL
-#define MISCS_REG_RESET_PL_HV_2_K2 \
+#define MISCS_REG_RESET_PL_HV_2_K2_E5 \
0x009150UL
#define DMAE_REG_DBG_SELECT \
0x00c510UL
@@ -647,15 +647,15 @@
0x0500b0UL
#define GRC_REG_DBG_FORCE_FRAME \
0x0500b4UL
-#define UMAC_REG_DBG_SELECT_K2 \
+#define UMAC_REG_DBG_SELECT_K2_E5 \
0x051094UL
-#define UMAC_REG_DBG_DWORD_ENABLE_K2 \
+#define UMAC_REG_DBG_DWORD_ENABLE_K2_E5 \
0x051098UL
-#define UMAC_REG_DBG_SHIFT_K2 \
+#define UMAC_REG_DBG_SHIFT_K2_E5 \
0x05109cUL
-#define UMAC_REG_DBG_FORCE_VALID_K2 \
+#define UMAC_REG_DBG_FORCE_VALID_K2_E5 \
0x0510a0UL
-#define UMAC_REG_DBG_FORCE_FRAME_K2 \
+#define UMAC_REG_DBG_FORCE_FRAME_K2_E5 \
0x0510a4UL
#define MCP2_REG_DBG_SELECT \
0x052400UL
@@ -717,15 +717,15 @@
0x1f0ba0UL
#define PRS_REG_DBG_FORCE_FRAME \
0x1f0ba4UL
-#define CNIG_REG_DBG_SELECT_K2 \
+#define CNIG_REG_DBG_SELECT_K2_E5 \
0x218254UL
-#define CNIG_REG_DBG_DWORD_ENABLE_K2 \
+#define CNIG_REG_DBG_DWORD_ENABLE_K2_E5 \
0x218258UL
-#define CNIG_REG_DBG_SHIFT_K2 \
+#define CNIG_REG_DBG_SHIFT_K2_E5 \
0x21825cUL
-#define CNIG_REG_DBG_FORCE_VALID_K2 \
+#define CNIG_REG_DBG_FORCE_VALID_K2_E5 \
0x218260UL
-#define CNIG_REG_DBG_FORCE_FRAME_K2 \
+#define CNIG_REG_DBG_FORCE_FRAME_K2_E5 \
0x218264UL
#define PRM_REG_DBG_SELECT \
0x2306a8UL
@@ -997,35 +997,35 @@
0x580710UL
#define CDU_REG_DBG_FORCE_FRAME \
0x580714UL
-#define WOL_REG_DBG_SELECT_K2 \
+#define WOL_REG_DBG_SELECT_K2_E5 \
0x600140UL
-#define WOL_REG_DBG_DWORD_ENABLE_K2 \
+#define WOL_REG_DBG_DWORD_ENABLE_K2_E5 \
0x600144UL
-#define WOL_REG_DBG_SHIFT_K2 \
+#define WOL_REG_DBG_SHIFT_K2_E5 \
0x600148UL
-#define WOL_REG_DBG_FORCE_VALID_K2 \
+#define WOL_REG_DBG_FORCE_VALID_K2_E5 \
0x60014cUL
-#define WOL_REG_DBG_FORCE_FRAME_K2 \
+#define WOL_REG_DBG_FORCE_FRAME_K2_E5 \
0x600150UL
-#define BMBN_REG_DBG_SELECT_K2 \
+#define BMBN_REG_DBG_SELECT_K2_E5 \
0x610140UL
-#define BMBN_REG_DBG_DWORD_ENABLE_K2 \
+#define BMBN_REG_DBG_DWORD_ENABLE_K2_E5 \
0x610144UL
-#define BMBN_REG_DBG_SHIFT_K2 \
+#define BMBN_REG_DBG_SHIFT_K2_E5 \
0x610148UL
-#define BMBN_REG_DBG_FORCE_VALID_K2 \
+#define BMBN_REG_DBG_FORCE_VALID_K2_E5 \
0x61014cUL
-#define BMBN_REG_DBG_FORCE_FRAME_K2 \
+#define BMBN_REG_DBG_FORCE_FRAME_K2_E5 \
0x610150UL
-#define NWM_REG_DBG_SELECT_K2 \
+#define NWM_REG_DBG_SELECT_K2_E5 \
0x8000ecUL
-#define NWM_REG_DBG_DWORD_ENABLE_K2 \
+#define NWM_REG_DBG_DWORD_ENABLE_K2_E5 \
0x8000f0UL
-#define NWM_REG_DBG_SHIFT_K2 \
+#define NWM_REG_DBG_SHIFT_K2_E5 \
0x8000f4UL
-#define NWM_REG_DBG_FORCE_VALID_K2 \
+#define NWM_REG_DBG_FORCE_VALID_K2_E5 \
0x8000f8UL
-#define NWM_REG_DBG_FORCE_FRAME_K2\
+#define NWM_REG_DBG_FORCE_FRAME_K2_E5 \
0x8000fcUL
#define PBF_REG_DBG_SELECT \
0xd80060UL
@@ -1247,35 +1247,35 @@
0x1901534UL
#define USEM_REG_DBG_FORCE_FRAME \
0x1901538UL
-#define NWS_REG_DBG_SELECT_K2 \
+#define NWS_REG_DBG_SELECT_K2_E5 \
0x700128UL
-#define NWS_REG_DBG_DWORD_ENABLE_K2 \
+#define NWS_REG_DBG_DWORD_ENABLE_K2_E5 \
0x70012cUL
-#define NWS_REG_DBG_SHIFT_K2 \
+#define NWS_REG_DBG_SHIFT_K2_E5 \
0x700130UL
-#define NWS_REG_DBG_FORCE_VALID_K2 \
+#define NWS_REG_DBG_FORCE_VALID_K2_E5 \
0x700134UL
-#define NWS_REG_DBG_FORCE_FRAME_K2 \
+#define NWS_REG_DBG_FORCE_FRAME_K2_E5 \
0x700138UL
-#define MS_REG_DBG_SELECT_K2 \
+#define MS_REG_DBG_SELECT_K2_E5 \
0x6a0228UL
-#define MS_REG_DBG_DWORD_ENABLE_K2 \
+#define MS_REG_DBG_DWORD_ENABLE_K2_E5 \
0x6a022cUL
-#define MS_REG_DBG_SHIFT_K2 \
+#define MS_REG_DBG_SHIFT_K2_E5 \
0x6a0230UL
-#define MS_REG_DBG_FORCE_VALID_K2 \
+#define MS_REG_DBG_FORCE_VALID_K2_E5 \
0x6a0234UL
-#define MS_REG_DBG_FORCE_FRAME_K2 \
+#define MS_REG_DBG_FORCE_FRAME_K2_E5 \
0x6a0238UL
-#define PCIE_REG_DBG_COMMON_SELECT_K2 \
+#define PCIE_REG_DBG_COMMON_SELECT_K2_E5 \
0x054398UL
-#define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2 \
+#define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5 \
0x05439cUL
-#define PCIE_REG_DBG_COMMON_SHIFT_K2 \
+#define PCIE_REG_DBG_COMMON_SHIFT_K2_E5 \
0x0543a0UL
-#define PCIE_REG_DBG_COMMON_FORCE_VALID_K2 \
+#define PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5 \
0x0543a4UL
-#define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2 \
+#define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5 \
0x0543a8UL
#define MISC_REG_RESET_PL_UA \
0x008050UL
@@ -1415,7 +1415,7 @@
0x1940000UL
#define SEM_FAST_REG_INT_RAM \
0x020000UL
-#define SEM_FAST_REG_INT_RAM_SIZE \
+#define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 \
20480
#define GRC_REG_TRACE_FIFO_VALID_DATA \
0x050064UL
@@ -1451,7 +1451,7 @@
0x238c30UL
#define MISCS_REG_BLOCK_256B_EN \
0x009074UL
-#define MCP_REG_SCRATCH_SIZE \
+#define MCP_REG_SCRATCH_SIZE_BB_K2 \
57344
#define MCP_REG_CPU_REG_FILE \
0xe05200UL
@@ -1485,35 +1485,35 @@
0x008c14UL
#define NWS_REG_NWS_CMU_K2 \
0x720000UL
-#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 \
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5 \
0x000680UL
-#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 \
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5 \
0x000684UL
-#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 \
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5 \
0x0006c0UL
-#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 \
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5 \
0x0006c4UL
-#define MS_REG_MS_CMU_K2 \
+#define MS_REG_MS_CMU_K2_E5 \
0x6a4000UL
-#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 \
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \
0x000208UL
-#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 \
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \
0x00020cUL
-#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 \
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \
0x000210UL
-#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 \
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \
0x000214UL
-#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 \
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \
0x000208UL
-#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 \
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \
0x00020cUL
-#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 \
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \
0x000210UL
-#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 \
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \
0x000214UL
-#define PHY_PCIE_REG_PHY0_K2 \
+#define PHY_PCIE_REG_PHY0_K2_E5 \
0x620000UL
-#define PHY_PCIE_REG_PHY1_K2 \
+#define PHY_PCIE_REG_PHY1_K2_E5 \
0x624000UL
#define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
#define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL
diff --git a/drivers/net/ethernet/qlogic/qed/qed_spq.c b/drivers/net/ethernet/qlogic/qed/qed_spq.c
index be48d9a..217b62a 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_spq.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_spq.c
@@ -215,7 +215,7 @@ static int qed_spq_fill_entry(struct qed_hwfn *p_hwfn,
static void qed_spq_hw_initialize(struct qed_hwfn *p_hwfn,
struct qed_spq *p_spq)
{
- struct core_conn_context *p_cxt;
+ struct e4_core_conn_context *p_cxt;
struct qed_cxt_info cxt_info;
u16 physical_q;
int rc;
@@ -233,11 +233,11 @@ static void qed_spq_hw_initialize(struct qed_hwfn *p_hwfn,
p_cxt = cxt_info.p_cxt;
SET_FIELD(p_cxt->xstorm_ag_context.flags10,
- XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN, 1);
+ E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN, 1);
SET_FIELD(p_cxt->xstorm_ag_context.flags1,
- XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE, 1);
+ E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE, 1);
SET_FIELD(p_cxt->xstorm_ag_context.flags9,
- XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN, 1);
+ E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN, 1);
/* QM physical queue */
physical_q = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB);
diff --git a/drivers/net/ethernet/qlogic/qed/qed_sriov.c b/drivers/net/ethernet/qlogic/qed/qed_sriov.c
index 3f40b1d..4fec5fc 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_sriov.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_sriov.c
@@ -1621,7 +1621,7 @@ static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
/* fill in pfdev info */
pfdev_info->chip_num = p_hwfn->cdev->chip_num;
pfdev_info->db_size = 0;
- pfdev_info->indices_per_sb = PIS_PER_SB;
+ pfdev_info->indices_per_sb = PIS_PER_SB_E4;
pfdev_info->capabilities = PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED |
PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE;
@@ -3582,11 +3582,11 @@ static void qed_iov_vf_pf_set_coalesce(struct qed_hwfn *p_hwfn,
qed_iov_vf_flr_poll_pbf(struct qed_hwfn *p_hwfn,
struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
{
- u32 cons[MAX_NUM_VOQS], distance[MAX_NUM_VOQS];
+ u32 cons[MAX_NUM_VOQS_E4], distance[MAX_NUM_VOQS_E4];
int i, cnt;
/* Read initial consumers & producers */
- for (i = 0; i < MAX_NUM_VOQS; i++) {
+ for (i = 0; i < MAX_NUM_VOQS_E4; i++) {
u32 prod;
cons[i] = qed_rd(p_hwfn, p_ptt,
@@ -3601,7 +3601,7 @@ static void qed_iov_vf_pf_set_coalesce(struct qed_hwfn *p_hwfn,
/* Wait for consumers to pass the producers */
i = 0;
for (cnt = 0; cnt < 50; cnt++) {
- for (; i < MAX_NUM_VOQS; i++) {
+ for (; i < MAX_NUM_VOQS_E4; i++) {
u32 tmp;
tmp = qed_rd(p_hwfn, p_ptt,
@@ -3611,7 +3611,7 @@ static void qed_iov_vf_pf_set_coalesce(struct qed_hwfn *p_hwfn,
break;
}
- if (i == MAX_NUM_VOQS)
+ if (i == MAX_NUM_VOQS_E4)
break;
msleep(20);
diff --git a/drivers/net/ethernet/qlogic/qede/qede_main.c b/drivers/net/ethernet/qlogic/qede/qede_main.c
index 90d79ae..9292ca2 100644
--- a/drivers/net/ethernet/qlogic/qede/qede_main.c
+++ b/drivers/net/ethernet/qlogic/qede/qede_main.c
@@ -1147,7 +1147,7 @@ static void qede_free_mem_sb(struct qede_dev *edev, struct qed_sb_info *sb_info,
static int qede_alloc_mem_sb(struct qede_dev *edev,
struct qed_sb_info *sb_info, u16 sb_id)
{
- struct status_block *sb_virt;
+ struct status_block_e4 *sb_virt;
dma_addr_t sb_phys;
int rc;
diff --git a/drivers/scsi/qedf/drv_fcoe_fw_funcs.c b/drivers/scsi/qedf/drv_fcoe_fw_funcs.c
index 7d91e53..bfa6a57 100644
--- a/drivers/scsi/qedf/drv_fcoe_fw_funcs.c
+++ b/drivers/scsi/qedf/drv_fcoe_fw_funcs.c
@@ -25,10 +25,10 @@ int init_initiator_rw_fcoe_task(struct fcoe_task_params *task_params,
u32 task_retry_id,
u8 fcp_cmd_payload[32])
{
- struct fcoe_task_context *ctx = task_params->context;
+ struct e4_fcoe_task_context *ctx = task_params->context;
+ struct e4_ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ystorm_fcoe_task_st_ctx *y_st_ctx;
struct tstorm_fcoe_task_st_ctx *t_st_ctx;
- struct ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct mstorm_fcoe_task_st_ctx *m_st_ctx;
u32 io_size, val;
bool slow_sgl;
@@ -112,10 +112,10 @@ int init_initiator_midpath_unsolicited_fcoe_task(
struct scsi_sgl_task_params *rx_sgl_task_params,
u8 fw_to_place_fc_header)
{
- struct fcoe_task_context *ctx = task_params->context;
+ struct e4_fcoe_task_context *ctx = task_params->context;
+ struct e4_ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ystorm_fcoe_task_st_ctx *y_st_ctx;
struct tstorm_fcoe_task_st_ctx *t_st_ctx;
- struct ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct mstorm_fcoe_task_st_ctx *m_st_ctx;
u32 val;
diff --git a/drivers/scsi/qedf/drv_fcoe_fw_funcs.h b/drivers/scsi/qedf/drv_fcoe_fw_funcs.h
index f9c50fa..b5c236e 100644
--- a/drivers/scsi/qedf/drv_fcoe_fw_funcs.h
+++ b/drivers/scsi/qedf/drv_fcoe_fw_funcs.h
@@ -13,7 +13,7 @@
struct fcoe_task_params {
/* Output parameter [set/filled by the HSI function] */
- struct fcoe_task_context *context;
+ struct e4_fcoe_task_context *context;
/* Output parameter [set/filled by the HSI function] */
struct fcoe_wqe *sqe;
diff --git a/drivers/scsi/qedf/qedf.h b/drivers/scsi/qedf/qedf.h
index 9bf7b22..c105a2e 100644
--- a/drivers/scsi/qedf/qedf.h
+++ b/drivers/scsi/qedf/qedf.h
@@ -129,7 +129,7 @@ struct qedf_ioreq {
struct delayed_work timeout_work;
struct completion tm_done;
struct completion abts_done;
- struct fcoe_task_context *task;
+ struct e4_fcoe_task_context *task;
struct fcoe_task_params *task_params;
struct scsi_sgl_task_params *sgl_task_params;
int idx;
@@ -465,7 +465,7 @@ extern void qedf_cmd_timer_set(struct qedf_ctx *qedf, struct qedf_ioreq *io_req,
unsigned int timer_msec);
extern int qedf_init_mp_req(struct qedf_ioreq *io_req);
extern void qedf_init_mp_task(struct qedf_ioreq *io_req,
- struct fcoe_task_context *task_ctx, struct fcoe_wqe *wqe);
+ struct e4_fcoe_task_context *task_ctx, struct fcoe_wqe *sqe);
extern u16 qedf_get_sqe_idx(struct qedf_rport *fcport);
extern void qedf_ring_doorbell(struct qedf_rport *fcport);
extern void qedf_process_els_compl(struct qedf_ctx *qedf, struct fcoe_cqe *cqe,
diff --git a/drivers/scsi/qedf/qedf_els.c b/drivers/scsi/qedf/qedf_els.c
index 59c18ca..aa22b11 100644
--- a/drivers/scsi/qedf/qedf_els.c
+++ b/drivers/scsi/qedf/qedf_els.c
@@ -19,7 +19,7 @@ static int qedf_initiate_els(struct qedf_rport *fcport, unsigned int op,
struct qedf_ioreq *els_req;
struct qedf_mp_req *mp_req;
struct fc_frame_header *fc_hdr;
- struct fcoe_task_context *task;
+ struct e4_fcoe_task_context *task;
int rc = 0;
uint32_t did, sid;
uint16_t xid;
diff --git a/drivers/scsi/qedf/qedf_io.c b/drivers/scsi/qedf/qedf_io.c
index ded3860..db895c1 100644
--- a/drivers/scsi/qedf/qedf_io.c
+++ b/drivers/scsi/qedf/qedf_io.c
@@ -579,7 +579,7 @@ static void qedf_build_fcp_cmnd(struct qedf_ioreq *io_req,
}
static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
- struct qedf_ioreq *io_req, struct fcoe_task_context *task_ctx,
+ struct qedf_ioreq *io_req, struct e4_fcoe_task_context *task_ctx,
struct fcoe_wqe *sqe)
{
enum fcoe_task_type task_type;
@@ -597,7 +597,7 @@ static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
/* Note init_initiator_rw_fcoe_task memsets the task context */
io_req->task = task_ctx;
- memset(task_ctx, 0, sizeof(struct fcoe_task_context));
+ memset(task_ctx, 0, sizeof(struct e4_fcoe_task_context));
memset(io_req->task_params, 0, sizeof(struct fcoe_task_params));
memset(io_req->sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
@@ -673,7 +673,7 @@ static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
}
void qedf_init_mp_task(struct qedf_ioreq *io_req,
- struct fcoe_task_context *task_ctx, struct fcoe_wqe *sqe)
+ struct e4_fcoe_task_context *task_ctx, struct fcoe_wqe *sqe)
{
struct qedf_mp_req *mp_req = &(io_req->mp_req);
struct qedf_rport *fcport = io_req->fcport;
@@ -691,7 +691,7 @@ void qedf_init_mp_task(struct qedf_ioreq *io_req,
memset(&tx_sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
memset(&rx_sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
- memset(task_ctx, 0, sizeof(struct fcoe_task_context));
+ memset(task_ctx, 0, sizeof(struct e4_fcoe_task_context));
memset(&task_fc_hdr, 0, sizeof(struct fcoe_tx_mid_path_params));
/* Setup the task from io_req for easy reference */
@@ -844,7 +844,7 @@ int qedf_post_io_req(struct qedf_rport *fcport, struct qedf_ioreq *io_req)
struct Scsi_Host *host = sc_cmd->device->host;
struct fc_lport *lport = shost_priv(host);
struct qedf_ctx *qedf = lport_priv(lport);
- struct fcoe_task_context *task_ctx;
+ struct e4_fcoe_task_context *task_ctx;
u16 xid;
enum fcoe_task_type req_type = 0;
struct fcoe_wqe *sqe;
@@ -1065,7 +1065,7 @@ void qedf_scsi_completion(struct qedf_ctx *qedf, struct fcoe_cqe *cqe,
struct qedf_ioreq *io_req)
{
u16 xid, rval;
- struct fcoe_task_context *task_ctx;
+ struct e4_fcoe_task_context *task_ctx;
struct scsi_cmnd *sc_cmd;
struct fcoe_cqe_rsp_info *fcp_rsp;
struct qedf_rport *fcport;
@@ -1722,7 +1722,7 @@ int qedf_initiate_cleanup(struct qedf_ioreq *io_req,
struct qedf_rport *fcport;
struct qedf_ctx *qedf;
uint16_t xid;
- struct fcoe_task_context *task;
+ struct e4_fcoe_task_context *task;
int tmo = 0;
int rc = SUCCESS;
unsigned long flags;
@@ -1835,7 +1835,7 @@ static int qedf_execute_tmf(struct qedf_rport *fcport, struct scsi_cmnd *sc_cmd,
uint8_t tm_flags)
{
struct qedf_ioreq *io_req;
- struct fcoe_task_context *task;
+ struct e4_fcoe_task_context *task;
struct qedf_ctx *qedf = fcport->qedf;
struct fc_lport *lport = qedf->lport;
int rc = 0;
diff --git a/drivers/scsi/qedf/qedf_main.c b/drivers/scsi/qedf/qedf_main.c
index 7c00645..09ad22d 100644
--- a/drivers/scsi/qedf/qedf_main.c
+++ b/drivers/scsi/qedf/qedf_main.c
@@ -1860,7 +1860,7 @@ static bool qedf_fp_has_work(struct qedf_fastpath *fp)
struct qedf_ctx *qedf = fp->qedf;
struct global_queue *que;
struct qed_sb_info *sb_info = fp->sb_info;
- struct status_block *sb = sb_info->sb_virt;
+ struct status_block_e4 *sb = sb_info->sb_virt;
u16 prod_idx;
/* Get the pointer to the global CQ this completion is on */
@@ -1887,7 +1887,7 @@ static bool qedf_process_completions(struct qedf_fastpath *fp)
{
struct qedf_ctx *qedf = fp->qedf;
struct qed_sb_info *sb_info = fp->sb_info;
- struct status_block *sb = sb_info->sb_virt;
+ struct status_block_e4 *sb = sb_info->sb_virt;
struct global_queue *que;
u16 prod_idx;
struct fcoe_cqe *cqe;
@@ -2352,12 +2352,12 @@ void qedf_fp_io_handler(struct work_struct *work)
static int qedf_alloc_and_init_sb(struct qedf_ctx *qedf,
struct qed_sb_info *sb_info, u16 sb_id)
{
- struct status_block *sb_virt;
+ struct status_block_e4 *sb_virt;
dma_addr_t sb_phys;
int ret;
sb_virt = dma_alloc_coherent(&qedf->pdev->dev,
- sizeof(struct status_block), &sb_phys, GFP_KERNEL);
+ sizeof(struct status_block_e4), &sb_phys, GFP_KERNEL);
if (!sb_virt) {
QEDF_ERR(&(qedf->dbg_ctx), "Status block allocation failed "
diff --git a/drivers/scsi/qedi/qedi_debugfs.c b/drivers/scsi/qedi/qedi_debugfs.c
index 39d7781..fd8a1ee 100644
--- a/drivers/scsi/qedi/qedi_debugfs.c
+++ b/drivers/scsi/qedi/qedi_debugfs.c
@@ -152,7 +152,7 @@ struct qedi_debugfs_ops qedi_debugfs_ops[] = {
{
struct qedi_fastpath *fp = NULL;
struct qed_sb_info *sb_info = NULL;
- struct status_block *sb = NULL;
+ struct status_block_e4 *sb = NULL;
struct global_queue *que = NULL;
int id;
u16 prod_idx;
@@ -168,7 +168,7 @@ struct qedi_debugfs_ops qedi_debugfs_ops[] = {
sb_info = fp->sb_info;
sb = sb_info->sb_virt;
prod_idx = (sb->pi_array[QEDI_PROTO_CQ_PROD_IDX] &
- STATUS_BLOCK_PROD_INDEX_MASK);
+ STATUS_BLOCK_E4_PROD_INDEX_MASK);
seq_printf(s, "SB PROD IDX: %d\n", prod_idx);
que = qedi->global_queues[fp->sb_id];
seq_printf(s, "DRV CONS IDX: %d\n", que->cq_cons_idx);
diff --git a/drivers/scsi/qedi/qedi_fw.c b/drivers/scsi/qedi/qedi_fw.c
index bd302d3..d62ed38 100644
--- a/drivers/scsi/qedi/qedi_fw.c
+++ b/drivers/scsi/qedi/qedi_fw.c
@@ -87,7 +87,7 @@ static void qedi_process_text_resp(struct qedi_ctx *qedi,
{
struct iscsi_conn *conn = qedi_conn->cls_conn->dd_data;
struct iscsi_session *session = conn->session;
- struct iscsi_task_context *task_ctx;
+ struct e4_iscsi_task_context *task_ctx;
struct iscsi_text_rsp *resp_hdr_ptr;
struct iscsi_text_response_hdr *cqe_text_response;
struct qedi_cmd *cmd;
@@ -260,7 +260,7 @@ static void qedi_process_login_resp(struct qedi_ctx *qedi,
{
struct iscsi_conn *conn = qedi_conn->cls_conn->dd_data;
struct iscsi_session *session = conn->session;
- struct iscsi_task_context *task_ctx;
+ struct e4_iscsi_task_context *task_ctx;
struct iscsi_login_rsp *resp_hdr_ptr;
struct iscsi_login_response_hdr *cqe_login_response;
struct qedi_cmd *cmd;
@@ -1017,7 +1017,7 @@ int qedi_send_iscsi_login(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct iscsi_login_req *login_hdr;
struct scsi_sge *resp_sge = NULL;
@@ -1037,8 +1037,9 @@ int qedi_send_iscsi_login(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
qedi_cmd->task_id = tid;
@@ -1119,7 +1120,7 @@ int qedi_send_iscsi_logout(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_logout *logout_hdr = NULL;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct qedi_cmd *qedi_cmd;
@@ -1137,8 +1138,9 @@ int qedi_send_iscsi_logout(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
qedi_cmd->task_id = tid;
@@ -1467,7 +1469,7 @@ static int qedi_send_iscsi_tmf(struct qedi_conn *qedi_conn,
struct iscsi_tmf_request_hdr tmf_pdu_header;
struct iscsi_task_params task_params;
struct qedi_ctx *qedi = qedi_conn->qedi;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_conn *conn = qedi_conn->cls_conn->dd_data;
struct iscsi_task *ctask;
struct iscsi_tm *tmf_hdr;
@@ -1490,8 +1492,9 @@ static int qedi_send_iscsi_tmf(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
qedi_cmd->task_id = tid;
@@ -1605,7 +1608,7 @@ int qedi_send_iscsi_text(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct iscsi_text *text_hdr;
struct scsi_sge *req_sge = NULL;
@@ -1627,8 +1630,9 @@ int qedi_send_iscsi_text(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
qedi_cmd->task_id = tid;
@@ -1705,7 +1709,7 @@ int qedi_send_iscsi_nopout(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
struct qedi_ctx *qedi = qedi_conn->qedi;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_nopout *nopout_hdr;
struct scsi_sge *resp_sge = NULL;
struct qedi_cmd *qedi_cmd;
@@ -1725,8 +1729,9 @@ int qedi_send_iscsi_nopout(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
qedi_cmd->task_id = tid;
@@ -2046,7 +2051,7 @@ int qedi_iscsi_send_ioreq(struct iscsi_task *task)
struct iscsi_task_params task_params;
struct iscsi_conn_params conn_params;
struct scsi_initiator_cmd_params cmd_params;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_cls_conn *cls_conn;
struct iscsi_scsi_req *hdr = (struct iscsi_scsi_req *)task->hdr;
enum iscsi_task_type task_type = MAX_ISCSI_TASK_TYPE;
@@ -2069,8 +2074,9 @@ int qedi_iscsi_send_ioreq(struct iscsi_task *task)
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
cmd->task_id = tid;
diff --git a/drivers/scsi/qedi/qedi_fw_api.c b/drivers/scsi/qedi/qedi_fw_api.c
index cf43b3f..f7a349c 100644
--- a/drivers/scsi/qedi/qedi_fw_api.c
+++ b/drivers/scsi/qedi/qedi_fw_api.c
@@ -203,7 +203,7 @@ static void init_default_iscsi_task(struct iscsi_task_params *task_params,
struct data_hdr *pdu_header,
enum iscsi_task_type task_type)
{
- struct iscsi_task_context *context;
+ struct e4_iscsi_task_context *context;
u16 index;
u32 val;
@@ -222,7 +222,7 @@ static void init_default_iscsi_task(struct iscsi_task_params *task_params,
cpu_to_le16(task_params->conn_icid);
SET_FIELD(context->ustorm_ag_context.flags1,
- USTORM_ISCSI_TASK_AG_CTX_R2T2RECV, 1);
+ E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV, 1);
context->ustorm_st_context.task_type = task_type;
context->ustorm_st_context.cq_rss_number = task_params->cq_rss_number;
@@ -252,10 +252,9 @@ void init_initiator_rw_cdb_ystorm_context(struct ystorm_iscsi_task_st_ctx *ystc,
static
void init_ustorm_task_contexts(struct ustorm_iscsi_task_st_ctx *ustorm_st_cxt,
- struct ustorm_iscsi_task_ag_ctx *ustorm_ag_cxt,
- u32 remaining_recv_len,
- u32 expected_data_transfer_len,
- u8 num_sges, bool tx_dif_conn_err_en)
+ struct e4_ustorm_iscsi_task_ag_ctx *ustorm_ag_cxt,
+ u32 remaining_recv_len, u32 expected_data_transfer_len,
+ u8 num_sges, bool tx_dif_conn_err_en)
{
u32 val;
@@ -265,12 +264,12 @@ void init_ustorm_task_contexts(struct ustorm_iscsi_task_st_ctx *ustorm_st_cxt,
ustorm_st_cxt->exp_data_transfer_len = val;
SET_FIELD(ustorm_st_cxt->reg1.reg1_map, ISCSI_REG1_NUM_SGES, num_sges);
SET_FIELD(ustorm_ag_cxt->flags2,
- USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN,
+ E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN,
tx_dif_conn_err_en ? 1 : 0);
}
static
-void set_rw_exp_data_acked_and_cont_len(struct iscsi_task_context *context,
+void set_rw_exp_data_acked_and_cont_len(struct e4_iscsi_task_context *context,
struct iscsi_conn_params *conn_params,
enum iscsi_task_type task_type,
u32 task_size,
@@ -469,7 +468,7 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
}
}
-static void set_local_completion_context(struct iscsi_task_context *context)
+static void set_local_completion_context(struct e4_iscsi_task_context *context)
{
SET_FIELD(context->ystorm_st_context.state.flags,
YSTORM_ISCSI_TASK_STATE_LOCAL_COMP, 1);
@@ -486,7 +485,7 @@ static int init_rw_iscsi_task(struct iscsi_task_params *task_params,
struct scsi_dif_task_params *dif_task_params)
{
u32 exp_data_transfer_len = conn_params->max_burst_length;
- struct iscsi_task_context *cxt;
+ struct e4_iscsi_task_context *cxt;
bool slow_io = false;
u32 task_size, val;
u8 num_sges = 0;
@@ -600,7 +599,7 @@ int init_initiator_login_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
- struct iscsi_task_context *cxt;
+ struct e4_iscsi_task_context *cxt;
cxt = task_params->context;
@@ -642,7 +641,7 @@ int init_initiator_nop_out_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_sgl_task_params,
struct scsi_sgl_task_params *rx_sgl_task_params)
{
- struct iscsi_task_context *cxt;
+ struct e4_iscsi_task_context *cxt;
cxt = task_params->context;
@@ -688,7 +687,7 @@ int init_initiator_logout_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
- struct iscsi_task_context *cxt;
+ struct e4_iscsi_task_context *cxt;
cxt = task_params->context;
@@ -743,7 +742,7 @@ int init_initiator_text_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
- struct iscsi_task_context *cxt;
+ struct e4_iscsi_task_context *cxt;
cxt = task_params->context;
diff --git a/drivers/scsi/qedi/qedi_fw_iscsi.h b/drivers/scsi/qedi/qedi_fw_iscsi.h
index b6f24f9..c3deb77 100644
--- a/drivers/scsi/qedi/qedi_fw_iscsi.h
+++ b/drivers/scsi/qedi/qedi_fw_iscsi.h
@@ -13,7 +13,7 @@
#include "qedi_fw_scsi.h"
struct iscsi_task_params {
- struct iscsi_task_context *context;
+ struct e4_iscsi_task_context *context;
struct iscsi_wqe *sqe;
u32 tx_io_size;
u32 rx_io_size;
diff --git a/drivers/scsi/qedi/qedi_iscsi.h b/drivers/scsi/qedi/qedi_iscsi.h
index 3247287..ea13151 100644
--- a/drivers/scsi/qedi/qedi_iscsi.h
+++ b/drivers/scsi/qedi/qedi_iscsi.h
@@ -182,7 +182,7 @@ struct qedi_cmd {
struct scsi_cmnd *scsi_cmd;
struct scatterlist *sg;
struct qedi_io_bdt io_tbl;
- struct iscsi_task_context request;
+ struct e4_iscsi_task_context request;
unsigned char *sense_buffer;
dma_addr_t sense_buffer_dma;
u16 task_id;
diff --git a/drivers/scsi/qedi/qedi_main.c b/drivers/scsi/qedi/qedi_main.c
index cccc34a..ce8d41c 100644
--- a/drivers/scsi/qedi/qedi_main.c
+++ b/drivers/scsi/qedi/qedi_main.c
@@ -339,12 +339,12 @@ static int qedi_init_uio(struct qedi_ctx *qedi)
static int qedi_alloc_and_init_sb(struct qedi_ctx *qedi,
struct qed_sb_info *sb_info, u16 sb_id)
{
- struct status_block *sb_virt;
+ struct status_block_e4 *sb_virt;
dma_addr_t sb_phys;
int ret;
sb_virt = dma_alloc_coherent(&qedi->pdev->dev,
- sizeof(struct status_block), &sb_phys,
+ sizeof(struct status_block_e4), &sb_phys,
GFP_KERNEL);
if (!sb_virt) {
QEDI_ERR(&qedi->dbg_ctx,
@@ -961,7 +961,7 @@ static bool qedi_process_completions(struct qedi_fastpath *fp)
{
struct qedi_ctx *qedi = fp->qedi;
struct qed_sb_info *sb_info = fp->sb_info;
- struct status_block *sb = sb_info->sb_virt;
+ struct status_block_e4 *sb = sb_info->sb_virt;
struct qedi_percpu_s *p = NULL;
struct global_queue *que;
u16 prod_idx;
@@ -1015,7 +1015,7 @@ static bool qedi_fp_has_work(struct qedi_fastpath *fp)
struct qedi_ctx *qedi = fp->qedi;
struct global_queue *que;
struct qed_sb_info *sb_info = fp->sb_info;
- struct status_block *sb = sb_info->sb_virt;
+ struct status_block_e4 *sb = sb_info->sb_virt;
u16 prod_idx;
barrier();
diff --git a/include/linux/qed/common_hsi.h b/include/linux/qed/common_hsi.h
index 4874c10..5aa9513 100644
--- a/include/linux/qed/common_hsi.h
+++ b/include/linux/qed/common_hsi.h
@@ -156,11 +156,11 @@
#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB)
-#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2)
+#define MAX_NUM_VOQS_E4 (MAX_NUM_VOQS_K2)
#define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
/* CIDs */
-#define NUM_OF_CONNECTION_TYPES (8)
+#define NUM_OF_CONNECTION_TYPES_E4 (8)
#define NUM_OF_LCIDS (320)
#define NUM_OF_LTIDS (320)
@@ -401,7 +401,7 @@
#define CAU_FSM_ETH_TX 1
/* Number of Protocol Indices per Status Block */
-#define PIS_PER_SB 12
+#define PIS_PER_SB_E4 12
#define CAU_HC_STOPPED_STATE 3
#define CAU_HC_DISABLE_STATE 4
@@ -1202,20 +1202,20 @@ struct rdif_task_context {
};
/* Status block structure */
-struct status_block {
- __le16 pi_array[PIS_PER_SB];
+struct status_block_e4 {
+ __le16 pi_array[PIS_PER_SB_E4];
__le32 sb_num;
-#define STATUS_BLOCK_SB_NUM_MASK 0x1FF
-#define STATUS_BLOCK_SB_NUM_SHIFT 0
-#define STATUS_BLOCK_ZERO_PAD_MASK 0x7F
-#define STATUS_BLOCK_ZERO_PAD_SHIFT 9
-#define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF
-#define STATUS_BLOCK_ZERO_PAD2_SHIFT 16
+#define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF
+#define STATUS_BLOCK_E4_SB_NUM_SHIFT 0
+#define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F
+#define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9
+#define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF
+#define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16
__le32 prod_index;
-#define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
-#define STATUS_BLOCK_PROD_INDEX_SHIFT 0
-#define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF
-#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
+#define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF
+#define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0
+#define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF
+#define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24
};
/* Tdif context */
diff --git a/include/linux/qed/fcoe_common.h b/include/linux/qed/fcoe_common.h
index e720a7b..52a1e8d 100644
--- a/include/linux/qed/fcoe_common.h
+++ b/include/linux/qed/fcoe_common.h
@@ -152,49 +152,49 @@ struct ystorm_fcoe_task_st_ctx {
u8 reserved2[8];
};
-struct ystorm_fcoe_task_ag_ctx {
+struct e4_ystorm_fcoe_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
-#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
-#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
-#define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
-#define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
-#define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
-#define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
+#define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
+#define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
-#define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
-#define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
-#define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
-#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
-#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
-#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
-#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
-#define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
-#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 reg0;
u8 byte3;
@@ -208,73 +208,73 @@ struct ystorm_fcoe_task_ag_ctx {
__le32 reg2;
};
-struct tstorm_fcoe_task_ag_ctx {
+struct e4_tstorm_fcoe_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
-#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
-#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
-#define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
+#define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
u8 flags1;
-#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
+#define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
+#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
+#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
+#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
u8 flags3;
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
-#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
+#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
+#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
+#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
+#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
u8 flags4;
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
-#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
-#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
-#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
+#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 cleanup_state;
__le16 last_sent_tid;
__le32 rec_rr_tov_exp_timeout;
@@ -354,49 +354,49 @@ struct tstorm_fcoe_task_st_ctx {
struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
};
-struct mstorm_fcoe_task_ag_ctx {
+struct e4_mstorm_fcoe_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 icid;
u8 flags0;
-#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
-#define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
-#define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
+#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
+#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
-#define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
-#define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
-#define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
-#define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
-#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
-#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
-#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
-#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 cleanup_state;
__le32 received_bytes;
u8 byte3;
@@ -442,56 +442,56 @@ struct mstorm_fcoe_task_st_ctx {
struct scsi_cached_sges data_desc;
};
-struct ustorm_fcoe_task_ag_ctx {
+struct e4_ustorm_fcoe_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
-#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
-#define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
+#define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
-#define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
u8 flags2;
-#define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
-#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
-#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
-#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
u8 flags3;
-#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
-#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
-#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 global_cq_num;
@@ -501,18 +501,18 @@ struct ustorm_fcoe_task_ag_ctx {
};
/* FCoE task context */
-struct fcoe_task_context {
+struct e4_fcoe_task_context {
struct ystorm_fcoe_task_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct tdif_task_context tdif_context;
- struct ystorm_fcoe_task_ag_ctx ystorm_ag_context;
- struct tstorm_fcoe_task_ag_ctx tstorm_ag_context;
+ struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context;
+ struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context;
struct timers_context timer_context;
struct tstorm_fcoe_task_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2];
- struct mstorm_fcoe_task_ag_ctx mstorm_ag_context;
+ struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context;
struct mstorm_fcoe_task_st_ctx mstorm_st_context;
- struct ustorm_fcoe_task_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context;
struct rdif_task_context rdif_context;
};
diff --git a/include/linux/qed/iscsi_common.h b/include/linux/qed/iscsi_common.h
index b8f8350..331b9c3 100644
--- a/include/linux/qed/iscsi_common.h
+++ b/include/linux/qed/iscsi_common.h
@@ -673,49 +673,49 @@ struct ystorm_iscsi_task_st_ctx {
union iscsi_task_hdr pdu_hdr;
};
-struct ystorm_iscsi_task_ag_ctx {
+struct e4_ystorm_iscsi_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 word0;
u8 flags0;
-#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
-#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
-#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
-#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 TTT;
u8 byte3;
@@ -723,49 +723,49 @@ struct ystorm_iscsi_task_ag_ctx {
__le16 word1;
};
-struct mstorm_iscsi_task_ag_ctx {
+struct e4_mstorm_iscsi_task_ag_ctx {
u8 cdu_validation;
u8 byte1;
__le16 task_cid;
u8 flags0;
-#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
u8 flags1;
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 reg0;
u8 byte3;
@@ -773,56 +773,56 @@ struct mstorm_iscsi_task_ag_ctx {
__le16 word1;
};
-struct ustorm_iscsi_task_ag_ctx {
+struct e4_ustorm_iscsi_task_ag_ctx {
u8 reserved;
u8 state;
__le16 icid;
u8 flags0;
-#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define USTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_USTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
u8 flags1;
-#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
-#define USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
+#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
u8 flags2;
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
-#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
-#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
+#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
u8 flags3;
-#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
-#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 rcv_cont_len;
@@ -907,14 +907,14 @@ struct ustorm_iscsi_task_st_ctx {
};
/* iscsi task context */
-struct iscsi_task_context {
+struct e4_iscsi_task_context {
struct ystorm_iscsi_task_st_ctx ystorm_st_context;
- struct ystorm_iscsi_task_ag_ctx ystorm_ag_context;
+ struct e4_ystorm_iscsi_task_ag_ctx ystorm_ag_context;
struct regpair ystorm_ag_padding[2];
struct tdif_task_context tdif_context;
- struct mstorm_iscsi_task_ag_ctx mstorm_ag_context;
+ struct e4_mstorm_iscsi_task_ag_ctx mstorm_ag_context;
struct regpair mstorm_ag_padding[2];
- struct ustorm_iscsi_task_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_iscsi_task_ag_ctx ustorm_ag_context;
struct mstorm_iscsi_task_st_ctx mstorm_st_context;
struct ustorm_iscsi_task_st_ctx ustorm_st_context;
struct rdif_task_context rdif_context;
@@ -1364,73 +1364,73 @@ struct ystorm_iscsi_stats_drv {
struct regpair iscsi_tx_total_pdu_cnt;
};
-struct tstorm_iscsi_task_ag_ctx {
+struct e4_tstorm_iscsi_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
-#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
-#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
u8 flags3;
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
u8 flags4;
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 byte2;
__le16 word1;
__le32 reg0;
diff --git a/include/linux/qed/qed_if.h b/include/linux/qed/qed_if.h
index 0301499..310442f 100644
--- a/include/linux/qed/qed_if.h
+++ b/include/linux/qed/qed_if.h
@@ -316,7 +316,7 @@ enum qed_int_mode {
};
struct qed_sb_info {
- struct status_block *sb_virt;
+ struct status_block_e4 *sb_virt;
dma_addr_t sb_phys;
u32 sb_ack; /* Last given ack */
u16 igu_sb_id;
@@ -939,7 +939,7 @@ static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
u16 rc = 0;
prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
- STATUS_BLOCK_PROD_INDEX_MASK;
+ STATUS_BLOCK_E4_PROD_INDEX_MASK;
if (sb_info->sb_ack != prod) {
sb_info->sb_ack = prod;
rc |= QED_SB_IDX;
--
1.8.3.1
Powered by blists - more mailing lists