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Message-ID: <201801120230.an91N2Ij%fengguang.wu@intel.com>
Date: Fri, 12 Jan 2018 02:33:33 +0800
From: kbuild test robot <fengguang.wu@...el.com>
To: Ganesh Goudar <ganeshgr@...lsio.com>
Cc: kbuild-all@...org, netdev@...r.kernel.org
Subject: [net-next:master 283/286]
drivers/net/ethernet/chelsio/cxgb4/sge.c:1412:47: sparse: cast from
restricted __sum16
tree: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git master
head: 532b5aa0b41ae908842166be4d17fffa53590bf0
commit: d0a1299c6bf7d80c8bb8e181f36a7c407a4cabca [283/286] cxgb4: add support for vxlan segmentation offload
reproduce:
# apt-get install sparse
git checkout d0a1299c6bf7d80c8bb8e181f36a7c407a4cabca
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
>> drivers/net/ethernet/chelsio/cxgb4/sge.c:1412:47: sparse: cast from restricted __sum16
>> drivers/net/ethernet/chelsio/cxgb4/sge.c:1412:44: sparse: incorrect type in assignment (different base types) @@ expected restricted __sum16 check @@ got unsignerestricted __sum16 check @@
drivers/net/ethernet/chelsio/cxgb4/sge.c:1412:44: expected restricted __sum16 check
drivers/net/ethernet/chelsio/cxgb4/sge.c:1412:44: got unsigned short <noident>
drivers/net/ethernet/chelsio/cxgb4/sge.c:2241:43: sparse: cast to restricted __be64
drivers/net/ethernet/chelsio/cxgb4/sge.c:2241:43: sparse: cast to restricted __be64
drivers/net/ethernet/chelsio/cxgb4/sge.c:2241:43: sparse: cast to restricted __be64
drivers/net/ethernet/chelsio/cxgb4/sge.c:2241:43: sparse: cast to restricted __be64
drivers/net/ethernet/chelsio/cxgb4/sge.c:2241:43: sparse: cast to restricted __be64
drivers/net/ethernet/chelsio/cxgb4/sge.c:2241:43: sparse: cast to restricted __be64
drivers/net/ethernet/chelsio/cxgb4/sge.c:2241:43: sparse: cast to restricted __be64
drivers/net/ethernet/chelsio/cxgb4/sge.c:2241:43: sparse: cast to restricted __be64
drivers/net/ethernet/chelsio/cxgb4/sge.c:2241:43: sparse: cast to restricted __be64
drivers/net/ethernet/chelsio/cxgb4/sge.c:2241:43: sparse: cast to restricted __be64
drivers/net/ethernet/chelsio/cxgb4/sge.c:1304:34: sparse: context imbalance in 't4_eth_xmit' - different lock contexts for basic block
drivers/net/ethernet/chelsio/cxgb4/sge.c:1795:28: sparse: context imbalance in 'service_ofldq' - unexpected unlock
vim +1412 drivers/net/ethernet/chelsio/cxgb4/sge.c
1344
1345 chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
1346 flits = calc_tx_flits(skb, chip_ver);
1347 ndesc = flits_to_desc(flits);
1348 credits = txq_avail(&q->q) - ndesc;
1349
1350 if (unlikely(credits < 0)) {
1351 eth_txq_stop(q);
1352 dev_err(adap->pdev_dev,
1353 "%s: Tx ring %u full while queue awake!\n",
1354 dev->name, qidx);
1355 if (ptp_enabled)
1356 spin_unlock(&adap->ptp_lock);
1357 return NETDEV_TX_BUSY;
1358 }
1359
1360 if (is_eth_imm(skb, chip_ver))
1361 immediate = true;
1362
1363 if (skb->encapsulation && chip_ver > CHELSIO_T5)
1364 tnl_type = cxgb_encap_offload_supported(skb);
1365
1366 if (!immediate &&
1367 unlikely(map_skb(adap->pdev_dev, skb, addr) < 0)) {
1368 q->mapping_err++;
1369 if (ptp_enabled)
1370 spin_unlock(&adap->ptp_lock);
1371 goto out_free;
1372 }
1373
1374 wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2));
1375 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
1376 eth_txq_stop(q);
1377 wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F;
1378 }
1379
1380 wr = (void *)&q->q.desc[q->q.pidx];
1381 wr->equiq_to_len16 = htonl(wr_mid);
1382 wr->r3 = cpu_to_be64(0);
1383 end = (u64 *)wr + flits;
1384
1385 len = immediate ? skb->len : 0;
1386 ssi = skb_shinfo(skb);
1387 if (ssi->gso_size) {
1388 struct cpl_tx_pkt_lso *lso = (void *)wr;
1389 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0;
1390 int l3hdr_len = skb_network_header_len(skb);
1391 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1392 struct cpl_tx_tnl_lso *tnl_lso = (void *)(wr + 1);
1393
1394 if (tnl_type)
1395 len += sizeof(*tnl_lso);
1396 else
1397 len += sizeof(*lso);
1398
1399 wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) |
1400 FW_WR_IMMDLEN_V(len));
1401 if (tnl_type) {
1402 struct iphdr *iph = ip_hdr(skb);
1403
1404 t6_fill_tnl_lso(skb, tnl_lso, tnl_type);
1405 cpl = (void *)(tnl_lso + 1);
1406 /* Driver is expected to compute partial checksum that
1407 * does not include the IP Total Length.
1408 */
1409 if (iph->version == 4) {
1410 iph->check = 0;
1411 iph->tot_len = 0;
> 1412 iph->check = (u16)(~ip_fast_csum((u8 *)iph,
1413 iph->ihl));
1414 }
1415 if (skb->ip_summed == CHECKSUM_PARTIAL)
1416 cntrl = hwcsum(adap->params.chip, skb);
1417 } else {
1418 lso->c.lso_ctrl = htonl(LSO_OPCODE_V(CPL_TX_PKT_LSO) |
1419 LSO_FIRST_SLICE_F | LSO_LAST_SLICE_F |
1420 LSO_IPV6_V(v6) |
1421 LSO_ETHHDR_LEN_V(eth_xtra_len / 4) |
1422 LSO_IPHDR_LEN_V(l3hdr_len / 4) |
1423 LSO_TCPHDR_LEN_V(tcp_hdr(skb)->doff));
1424 lso->c.ipid_ofst = htons(0);
1425 lso->c.mss = htons(ssi->gso_size);
1426 lso->c.seqno_offset = htonl(0);
1427 if (is_t4(adap->params.chip))
1428 lso->c.len = htonl(skb->len);
1429 else
1430 lso->c.len =
1431 htonl(LSO_T5_XFER_SIZE_V(skb->len));
1432 cpl = (void *)(lso + 1);
1433
1434 if (CHELSIO_CHIP_VERSION(adap->params.chip)
1435 <= CHELSIO_T5)
1436 cntrl = TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1437 else
1438 cntrl = T6_TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1439
1440 cntrl |= TXPKT_CSUM_TYPE_V(v6 ?
1441 TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1442 TXPKT_IPHDR_LEN_V(l3hdr_len);
1443 }
1444 q->tso++;
1445 q->tx_cso += ssi->gso_segs;
1446 } else {
1447 len += sizeof(*cpl);
1448 if (ptp_enabled)
1449 op = FW_PTP_TX_PKT_WR;
1450 else
1451 op = FW_ETH_TX_PKT_WR;
1452 wr->op_immdlen = htonl(FW_WR_OP_V(op) |
1453 FW_WR_IMMDLEN_V(len));
1454 cpl = (void *)(wr + 1);
1455 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1456 cntrl = hwcsum(adap->params.chip, skb) |
1457 TXPKT_IPCSUM_DIS_F;
1458 q->tx_cso++;
1459 }
1460 }
1461
1462 if (skb_vlan_tag_present(skb)) {
1463 q->vlan_ins++;
1464 cntrl |= TXPKT_VLAN_VLD_F | TXPKT_VLAN_V(skb_vlan_tag_get(skb));
1465 #ifdef CONFIG_CHELSIO_T4_FCOE
1466 if (skb->protocol == htons(ETH_P_FCOE))
1467 cntrl |= TXPKT_VLAN_V(
1468 ((skb->priority & 0x7) << VLAN_PRIO_SHIFT));
1469 #endif /* CONFIG_CHELSIO_T4_FCOE */
1470 }
1471
1472 ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) |
1473 TXPKT_PF_V(adap->pf);
1474 if (ptp_enabled)
1475 ctrl0 |= TXPKT_TSTAMP_F;
1476 #ifdef CONFIG_CHELSIO_T4_DCB
1477 if (is_t4(adap->params.chip))
1478 ctrl0 |= TXPKT_OVLAN_IDX_V(q->dcb_prio);
1479 else
1480 ctrl0 |= TXPKT_T5_OVLAN_IDX_V(q->dcb_prio);
1481 #endif
1482 cpl->ctrl0 = htonl(ctrl0);
1483 cpl->pack = htons(0);
1484 cpl->len = htons(skb->len);
1485 cpl->ctrl1 = cpu_to_be64(cntrl);
1486
1487 if (immediate) {
1488 inline_tx_skb(skb, &q->q, cpl + 1);
1489 dev_consume_skb_any(skb);
1490 } else {
1491 int last_desc;
1492
1493 write_sgl(skb, &q->q, (struct ulptx_sgl *)(cpl + 1), end, 0,
1494 addr);
1495 skb_orphan(skb);
1496
1497 last_desc = q->q.pidx + ndesc - 1;
1498 if (last_desc >= q->q.size)
1499 last_desc -= q->q.size;
1500 q->q.sdesc[last_desc].skb = skb;
1501 q->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1);
1502 }
1503
1504 txq_advance(&q->q, ndesc);
1505
1506 ring_tx_db(adap, &q->q, ndesc);
1507 if (ptp_enabled)
1508 spin_unlock(&adap->ptp_lock);
1509 return NETDEV_TX_OK;
1510 }
1511
---
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