netdev - Re: [PATCH net-next 0/2] cxgb4: speed up reading on-chip memory

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Message-Id: <20180114.121747.434455459277472523.davem@davemloft.net>
Date:   Sun, 14 Jan 2018 12:17:47 -0500 (EST)
From:   David Miller <davem@...emloft.net>
To:     rahul.lakkireddy@...lsio.com
Cc:     netdev@...r.kernel.org, ganeshgr@...lsio.com,
        nirranjan@...lsio.com, indranil@...lsio.com
Subject: Re: [PATCH net-next 0/2] cxgb4: speed up reading on-chip memory

From: Rahul Lakkireddy <rahul.lakkireddy@...lsio.com>
Date: Sun, 14 Jan 2018 15:02:03 +0530

> This series of patches speed up reading on-chip memory (EDC and MC)
> by using AVX intrinsic instructions when available.
> 
> Patch 1 exports callback to register supported intrinsic instructions
> when available.  Also rework logic to read EDC and MC.
> 
> Patch 2 adds AVX CPU intrinsic instructions to read EDC and MC
> 256-bits at a time.  Also fallback to regular 32-bit reads, if AVX is
> not available.

This violates things on several levels.

IO mappings are a special __iomem type because you _CANNOT_
dereference them directly.

This means you cannot feed them into normal C dereferences
or normal loads or stores.

The whole point is that if the layout and format of the
__iomem pointer changes, or if some special kind of access
is necessary, no driver code needs to change.

But if you start adding direct AVX instruction loads and
stores of these pointers, things are going to break in the
future.

Sorry, there is no way I am applying this patch set.

Thanks.