netdev - [PATCH 2/2] ixgbe: Set rss key in order.

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Message-Id: <1516721041-82282-2-git-send-email-xiangxia.m.yue@gmail.com>
Date:   Tue, 23 Jan 2018 07:24:01 -0800
From:   Tonghao Zhang <xiangxia.m.yue@...il.com>
To:     jeffrey.t.kirsher@...el.com
Cc:     netdev@...r.kernel.org, Tonghao Zhang <xiangxia.m.yue@...il.com>
Subject: [PATCH 2/2] ixgbe: Set rss key in order.

If we use ethtool to set rss key, for example,
we except 0x6d is K[0], and 0x5a is K[1]. But
the ixgbe driver set the 0xda is K[0].

ethtool -X eth0 hkey 6d:5a:56:da:25:5b:0e:c2:41:67:25:3d
	:43:a3:8f:b0:d0:ca:2b:cb:ae:7b:30:b4:77:cb:2d:a3
	:80:30:f2:0c:6a:42:b7:3b:be:ac:01:fa

The key is the original Microsoft's key.

7.1.2.8.1 RSS Hash Function: (82599 datasheet)
Given an array K with k bytes, our nomenclature assumes
that the array is laid out as follows:

K[0] K[1] K[2] ... K[k-1]

K[0] is the left-most byte, and the MSB of K[0] is the
left-most bit. K[k-1] is the right-most byte, and the
LSB of K[k-1] is the right-most bit.

8.2.3.7.14 RSS Random Key Register:
The K[0] is the 7:0 bit of RSSRK (RSS Random Key Register).

Signed-off-by: Tonghao Zhang <xiangxia.m.yue@...il.com>
---
 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 95aba97..0ca2e0e 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -3777,10 +3777,18 @@ u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
 void ixgbe_store_key(struct ixgbe_adapter *adapter)
 {
 	struct ixgbe_hw *hw = &adapter->hw;
-	int i;
+	u8 *rss_key = (u8 *)adapter->rss_key;
+	u32 key, i;

-	for (i = 0; i < 10; i++)
-		IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
+	/* Fill out hash function seeds */
+	for (i = 0; i < 10; i++) {
+		key  = rss_key[(i * 4)];
+		key |= rss_key[(i * 4) + 1] << 8;
+		key |= rss_key[(i * 4) + 2] << 16;
+		key |= rss_key[(i * 4) + 3] << 24;
+
+		IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), key);
+	}
 }

 /**
-- 
1.8.3.1