Message-ID: <D5C2FD580325C2409E11CD8571E1431C0180B5FD@de02wembxa.internal.synopsys.com>
Date:   Thu, 1 Feb 2018 14:44:24 +0000
From:   Joao Pinto <Joao.Pinto@...opsys.com>
To:     Jose Abreu <Jose.Abreu@...opsys.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
CC:     Jose Abreu <Jose.Abreu@...opsys.com>,
        "David S. Miller" <davem@...emloft.net>,
        Giuseppe Cavallaro <peppe.cavallaro@...com>,
        Alexandre Torgue <alexandre.torgue@...com>
Subject: RE: [PATCH net-next 2/2] net: stmmac: Add support for DWMAC5 and
 implement Safety Features

Looking great!

-----Original Message-----
From: Jose Abreu [mailto:joabreu@...opsys.com] 
Sent: Thursday, February 1, 2018 2:42 PM
To: netdev@...r.kernel.org
Cc: Jose Abreu <joabreu@...opsys.com>; David S. Miller <davem@...emloft.net>; Joao Pinto <jpinto@...opsys.com>; Giuseppe Cavallaro <peppe.cavallaro@...com>; Alexandre Torgue <alexandre.torgue@...com>
Subject: [PATCH net-next 2/2] net: stmmac: Add support for DWMAC5 and implement Safety Features

This adds initial suport for DWMAC5 and implements the Automotive Safety Package which is available from core version 5.10.

The Automotive Safety Pacakge (also called Safety Features) offers us with error protection in the core by implementing ECC Protection in memories, on-chip data path parity protection, FSM parity and timeout protection and Application/CSR interface timeout protection.

In case of an uncorrectable error we call stmmac_global_err() and reconfigure the whole core.

Signed-off-by: Jose Abreu <joabreu@...opsys.com>
Cc: David S. Miller <davem@...emloft.net>
Cc: Joao Pinto <jpinto@...opsys.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@...com>
Cc: Alexandre Torgue <alexandre.torgue@...com>
---
 drivers/net/ethernet/stmicro/stmmac/Makefile      |    2 +-
 drivers/net/ethernet/stmicro/stmmac/common.h      |    8 +
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h      |    4 +
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c |   38 +++-
 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c  |    6 +
 drivers/net/ethernet/stmicro/stmmac/dwmac5.c      |  242 +++++++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac5.h      |   49 ++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c |   35 +++
 8 files changed, 382 insertions(+), 2 deletions(-)  create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac5.c
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac5.h

diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index ff3f83b..972e4ef 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -4,7 +4,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o	\
 	      chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o	\
 	      dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o	\
 	      mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o	\
-	      dwmac4_dma.o dwmac4_lib.o dwmac4_core.o $(stmmac-y)
+	      dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o $(stmmac-y)
 
 # Ordering matters. Generic driver must be last.
 obj-$(CONFIG_STMMAC_PLATFORM)	+= stmmac-platform.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 2ffe76c..7bbd7eb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -38,6 +38,8 @@
 #define	DWMAC_CORE_3_40	0x34
 #define	DWMAC_CORE_3_50	0x35
 #define	DWMAC_CORE_4_00	0x40
+#define DWMAC_CORE_5_00 0x50
+#define DWMAC_CORE_5_10 0x51
 #define STMMAC_CHAN0	0	/* Always supported and default for all chips */
 
 /* These need to be power of two, and >= 4 */ @@ -336,6 +338,8 @@ struct dma_features {
 	/* TX and RX FIFO sizes */
 	unsigned int tx_fifo_size;
 	unsigned int rx_fifo_size;
+	/* Automotive Safety Package */
+	unsigned int asp;
 };
 
 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */ @@ -532,6 +536,10 @@ struct stmmac_ops {
 			     bool loopback);
 	void (*pcs_rane)(void __iomem *ioaddr, bool restart);
 	void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
+	/* Safety Features */
+	int (*safety_feat_config)(void __iomem *ioaddr, unsigned int asp);
+	bool (*safety_feat_irq_status)(struct net_device *ndev,
+			void __iomem *ioaddr, unsigned int asp);
 };
 
 /* PTP and HW Timer helpers */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index 789dad8..afe9834 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -39,6 +39,7 @@
 #define GMAC_HW_FEATURE0		0x0000011c
 #define GMAC_HW_FEATURE1		0x00000120
 #define GMAC_HW_FEATURE2		0x00000124
+#define GMAC_HW_FEATURE3		0x00000128
 #define GMAC_MDIO_ADDR			0x00000200
 #define GMAC_MDIO_DATA			0x00000204
 #define GMAC_ADDR_HIGH(reg)		(0x300 + reg * 8)
@@ -192,6 +193,9 @@ enum power_event {
 #define GMAC_HW_FEAT_TXQCNT		GENMASK(9, 6)
 #define GMAC_HW_FEAT_RXQCNT		GENMASK(3, 0)
 
+/* MAC HW features3 bitmap */
+#define GMAC_HW_FEAT_ASP		GENMASK(29, 28)
+
 /* MAC HW ADDR regs */
 #define GMAC_HI_DCS			GENMASK(18, 16)
 #define GMAC_HI_DCS_SHIFT		16
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index ed222b2..5a24a6f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -20,6 +20,7 @@
 #include <net/dsa.h>
 #include "stmmac_pcs.h"
 #include "dwmac4.h"
+#include "dwmac5.h"
 
 static void dwmac4_core_init(struct mac_device_info *hw,
 			     struct net_device *dev)
@@ -767,6 +768,39 @@ static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 	.set_filter = dwmac4_set_filter,
 };
 
+static const struct stmmac_ops dwmac510_ops = {
+	.core_init = dwmac4_core_init,
+	.set_mac = stmmac_dwmac4_set_mac,
+	.rx_ipc = dwmac4_rx_ipc_enable,
+	.rx_queue_enable = dwmac4_rx_queue_enable,
+	.rx_queue_prio = dwmac4_rx_queue_priority,
+	.tx_queue_prio = dwmac4_tx_queue_priority,
+	.rx_queue_routing = dwmac4_tx_queue_routing,
+	.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
+	.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
+	.set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
+	.map_mtl_to_dma = dwmac4_map_mtl_dma,
+	.config_cbs = dwmac4_config_cbs,
+	.dump_regs = dwmac4_dump_regs,
+	.host_irq_status = dwmac4_irq_status,
+	.host_mtl_irq_status = dwmac4_irq_mtl_status,
+	.flow_ctrl = dwmac4_flow_ctrl,
+	.pmt = dwmac4_pmt,
+	.set_umac_addr = dwmac4_set_umac_addr,
+	.get_umac_addr = dwmac4_get_umac_addr,
+	.set_eee_mode = dwmac4_set_eee_mode,
+	.reset_eee_mode = dwmac4_reset_eee_mode,
+	.set_eee_timer = dwmac4_set_eee_timer,
+	.set_eee_pls = dwmac4_set_eee_pls,
+	.pcs_ctrl_ane = dwmac4_ctrl_ane,
+	.pcs_rane = dwmac4_rane,
+	.pcs_get_adv_lp = dwmac4_get_adv_lp,
+	.debug = dwmac4_debug,
+	.set_filter = dwmac4_set_filter,
+	.safety_feat_config = dwmac5_safety_feat_config,
+	.safety_feat_irq_status = dwmac5_safety_feat_irq_status, };
+
 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 				     int perfect_uc_entries, int *synopsys_id)  { @@ -807,7 +841,9 @@ struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 	else
 		mac->dma = &dwmac4_dma_ops;
 
-	if (*synopsys_id >= DWMAC_CORE_4_00)
+	if (*synopsys_id >= DWMAC_CORE_5_10)
+		mac->mac = &dwmac510_ops;
+	else if (*synopsys_id >= DWMAC_CORE_4_00)
 		mac->mac = &dwmac410_ops;
 	else
 		mac->mac = &dwmac4_ops;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index c110f68..d37d457 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -373,6 +373,12 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr,
 
 	/* IEEE 1588-2002 */
 	dma_cap->time_stamp = 0;
+
+	/* MAC HW feature3 */
+	hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);
+
+	/* 5.10 Features */
+	dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
 }
 
 /* Enable/disable TSO feature and set MSS */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac5.c b/drivers/net/ethernet/stmicro/stmmac/dwmac5.c
new file mode 100644
index 0000000..f751cd8
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac5.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT) // Copyright (c) 2017 
+Synopsys, Inc. and/or its affiliates.
+// stmmac Support for 5.xx Ethernet QoS cores
+
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+#include "common.h"
+#include "dwmac4.h"
+#include "dwmac5.h"
+
+static void dwmac5_log_error(struct net_device *ndev, u32 value, bool corr,
+		const char *module_name, const char **errors_str) {
+	unsigned long loc, mask;
+
+	mask = value;
+	for_each_set_bit(loc, &mask, 32) {
+		netdev_err(ndev, "Found %s error in %s: '%s'\n", corr ?
+				"correctable" : "uncorrectable", module_name,
+				errors_str[loc]);
+	}
+}
+
+static const char *dwmac5_mac_errors[32] = {
+	"ATPES: Application Transmit Interface Parity Check Error",
+	"TPES: TSO Data Path Parity Check Error",
+	"RDPES: Read Descriptor Parity Check Error",
+	"MPES: MTL Data Path Parity Check Error",
+	"MTSPES: MTL TX Status Data Path Parity Check Error",
+	"ARPES: Application Receive Interface Data Path Parity Check Error",
+	"CWPES: CSR Write Data Path Parity Check Error",
+	"ASRPES: AXI Slave Read Data Path Parity Check Error",
+	"TTES: TX FSM Timeout Error",
+	"RTES: RX FSM Timeout Error",
+	"CTES: CSR FSM Timeout Error",
+	"ATES: APP FSM Timeout Error",
+	"PTES: PTP FSM Timeout Error",
+	"T125ES: TX125 FSM Timeout Error",
+	"R125ES: RX125 FSM Timeout Error",
+	"RVCTES: REV MDC FSM Timeout Error",
+	"MSTTES: Master Read/Write Timeout Error",
+	"SLVTES: Slave Read/Write Timeout Error",
+	"ATITES: Application Timeout on ATI Interface Error",
+	"ARITES: Application Timeout on ARI Interface Error",
+	"Unknown Error", /* 20 */
+	"Unknown Error", /* 21 */
+	"Unknown Error", /* 22 */
+	"Unknown Error", /* 23 */
+	"FSMPES: FSM State Parity Error",
+	"Unknown Error", /* 25 */
+	"Unknown Error", /* 26 */
+	"Unknown Error", /* 27 */
+	"Unknown Error", /* 28 */
+	"Unknown Error", /* 29 */
+	"Unknown Error", /* 30 */
+	"Unknown Error", /* 31 */
+};
+
+static bool dwmac5_handle_mac_err(struct net_device *ndev,
+		void __iomem *ioaddr, bool correctable) {
+	u32 value;
+
+	value = readl(ioaddr + MAC_DPP_FSM_INT_STATUS);
+	writel(value, ioaddr + MAC_DPP_FSM_INT_STATUS);
+
+	dwmac5_log_error(ndev, value, correctable, "MAC", dwmac5_mac_errors);
+	return !correctable;
+}
+
+static const char *dwmac5_mtl_errors[32] = {
+	"TXCES: MTL TX Memory Error",
+	"TXAMS: MTL TX Memory Address Mismatch Error",
+	"TXUES: MTL TX Memory Error",
+	"Unknown Error", /* 3 */
+	"RXCES: MTL RX Memory Error",
+	"RXAMS: MTL RX Memory Address Mismatch Error",
+	"RXUES: MTL RX Memory Error",
+	"Unknown Error", /* 7 */
+	"ECES: MTL EST Memory Error",
+	"EAMS: MTL EST Memory Address Mismatch Error",
+	"EUES: MTL EST Memory Error",
+	"Unknown Error", /* 11 */
+	"RPCES: MTL RX Parser Memory Error",
+	"RPAMS: MTL RX Parser Memory Address Mismatch Error",
+	"RPUES: MTL RX Parser Memory Error",
+	"Unknown Error", /* 15 */
+	"Unknown Error", /* 16 */
+	"Unknown Error", /* 17 */
+	"Unknown Error", /* 18 */
+	"Unknown Error", /* 19 */
+	"Unknown Error", /* 20 */
+	"Unknown Error", /* 21 */
+	"Unknown Error", /* 22 */
+	"Unknown Error", /* 23 */
+	"Unknown Error", /* 24 */
+	"Unknown Error", /* 25 */
+	"Unknown Error", /* 26 */
+	"Unknown Error", /* 27 */
+	"Unknown Error", /* 28 */
+	"Unknown Error", /* 29 */
+	"Unknown Error", /* 30 */
+	"Unknown Error", /* 31 */
+};
+
+static bool dwmac5_handle_mtl_err(struct net_device *ndev,
+		void __iomem *ioaddr, bool correctable) {
+	u32 value;
+
+	value = readl(ioaddr + MTL_ECC_INT_STATUS);
+	writel(value, ioaddr + MTL_ECC_INT_STATUS);
+
+	dwmac5_log_error(ndev, value, correctable, "MTL", dwmac5_mtl_errors);
+	return !correctable;
+}
+
+static const char *dwmac5_dma_errors[32] = {
+	"TCES: DMA TSO Memory Error",
+	"TAMS: DMA TSO Memory Address Mismatch Error",
+	"TUES: DMA TSO Memory Error",
+	"Unknown Error", /* 3 */
+	"Unknown Error", /* 4 */
+	"Unknown Error", /* 5 */
+	"Unknown Error", /* 6 */
+	"Unknown Error", /* 7 */
+	"Unknown Error", /* 8 */
+	"Unknown Error", /* 9 */
+	"Unknown Error", /* 10 */
+	"Unknown Error", /* 11 */
+	"Unknown Error", /* 12 */
+	"Unknown Error", /* 13 */
+	"Unknown Error", /* 14 */
+	"Unknown Error", /* 15 */
+	"Unknown Error", /* 16 */
+	"Unknown Error", /* 17 */
+	"Unknown Error", /* 18 */
+	"Unknown Error", /* 19 */
+	"Unknown Error", /* 20 */
+	"Unknown Error", /* 21 */
+	"Unknown Error", /* 22 */
+	"Unknown Error", /* 23 */
+	"Unknown Error", /* 24 */
+	"Unknown Error", /* 25 */
+	"Unknown Error", /* 26 */
+	"Unknown Error", /* 27 */
+	"Unknown Error", /* 28 */
+	"Unknown Error", /* 29 */
+	"Unknown Error", /* 30 */
+	"Unknown Error", /* 31 */
+};
+
+static bool dwmac5_handle_dma_err(struct net_device *ndev,
+		void __iomem *ioaddr, bool correctable) {
+	u32 value;
+
+	value = readl(ioaddr + DMA_ECC_INT_STATUS);
+	writel(value, ioaddr + DMA_ECC_INT_STATUS);
+
+	dwmac5_log_error(ndev, value, correctable, "DMA", dwmac5_dma_errors);
+	return !correctable;
+}
+
+int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp) {
+	u32 value;
+
+	if (!asp)
+		return -EINVAL;
+
+	/* 1. Enable Safety Features */
+	value = readl(ioaddr + MTL_ECC_CONTROL);
+	value |= TSOEE; /* TSO ECC */
+	value |= MRXPEE; /* MTL RX Parser ECC */
+	value |= MESTEE; /* MTL EST ECC */
+	value |= MRXEE; /* MTL RX FIFO ECC */
+	value |= MTXEE; /* MTL TX FIFO ECC */
+	writel(value, ioaddr + MTL_ECC_CONTROL);
+
+	/* 2. Enable MTL Safety Interrupts */
+	value = readl(ioaddr + MTL_ECC_INT_ENABLE);
+	value |= RPCEIE; /* RX Parser Memory Correctable Error */
+	value |= ECEIE; /* EST Memory Correctable Error */
+	value |= RXCEIE; /* RX Memory Correctable Error */
+	value |= TXCEIE; /* TX Memory Correctable Error */
+	writel(value, ioaddr + MTL_ECC_INT_ENABLE);
+
+	/* 3. Enable DMA Safety Interrupts */
+	value = readl(ioaddr + DMA_ECC_INT_ENABLE);
+	value |= TCEIE; /* TSO Memory Correctable Error */
+	writel(value, ioaddr + DMA_ECC_INT_ENABLE);
+
+	/* Only ECC Protection for External Memory feature is selected */
+	if (asp <= 0x1)
+		return 0;
+
+	/* 5. Enable Parity and Timeout for FSM */
+	value = readl(ioaddr + MAC_FSM_CONTROL);
+	value |= PRTYEN; /* FSM Parity Feature */
+	value |= TMOUTEN; /* FSM Timeout Feature */
+	writel(value, ioaddr + MAC_FSM_CONTROL);
+
+	/* 4. Enable Data Parity Protection */
+	value = readl(ioaddr + MTL_DPP_CONTROL);
+	value |= EDPP;
+	writel(value, ioaddr + MTL_DPP_CONTROL);
+
+	/*
+	 * All the Automotive Safety features are selected without the "Parity
+	 * Port Enable for external interface" feature.
+	 */
+	if (asp <= 0x2)
+		return 0;
+
+	value |= EPSI;
+	writel(value, ioaddr + MTL_DPP_CONTROL);
+	return 0;
+}
+
+bool dwmac5_safety_feat_irq_status(struct net_device *ndev,
+		void __iomem *ioaddr, unsigned int asp) {
+	bool ret = false;
+	u32 mtl, dma;
+
+	if (!asp)
+		return false;
+
+	mtl = readl(ioaddr + MTL_SAFETY_INT_STATUS);
+	dma = readl(ioaddr + DMA_SAFETY_INT_STATUS);
+
+	if ((mtl & MCSIS) || (dma & MCSIS))
+		ret |= dwmac5_handle_mac_err(ndev, ioaddr, false);
+	if ((mtl & (MEUIS | MECIS)) || (dma & (MSUIS | MSCIS)))
+		ret |= dwmac5_handle_mtl_err(ndev, ioaddr,
+				(mtl & MECIS) || (dma & MSCIS));
+	if (dma & (DEUIS | DECIS))
+		ret |= dwmac5_handle_dma_err(ndev, ioaddr, dma & DECIS);
+
+	return ret;
+}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac5.h b/drivers/net/ethernet/stmicro/stmmac/dwmac5.h
new file mode 100644
index 0000000..debbb8a
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac5.h
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT) // Copyright (c) 2017 
+Synopsys, Inc. and/or its affiliates.
+// stmmac Support for 5.xx Ethernet QoS cores
+
+#ifndef __DWMAC5_H__
+#define __DWMAC5_H__
+
+#define MAC_DPP_FSM_INT_STATUS		0x00000140
+#define MAC_AXI_SLV_DPE_ADDR_STATUS	0x00000144
+#define MAC_FSM_CONTROL			0x00000148
+#define PRTYEN				BIT(1)
+#define TMOUTEN				BIT(0)
+
+#define MTL_ECC_CONTROL			0x00000cc0
+#define TSOEE				BIT(4)
+#define MRXPEE				BIT(3)
+#define MESTEE				BIT(2)
+#define MRXEE				BIT(1)
+#define MTXEE				BIT(0)
+
+#define MTL_SAFETY_INT_STATUS		0x00000cc4
+#define MCSIS				BIT(31)
+#define MEUIS				BIT(1)
+#define MECIS				BIT(0)
+#define MTL_ECC_INT_ENABLE		0x00000cc8
+#define RPCEIE				BIT(12)
+#define ECEIE				BIT(8)
+#define RXCEIE				BIT(4)
+#define TXCEIE				BIT(0)
+#define MTL_ECC_INT_STATUS		0x00000ccc
+#define MTL_DPP_CONTROL			0x00000ce0
+#define EPSI				BIT(2)
+#define OPE				BIT(1)
+#define EDPP				BIT(0)
+
+#define DMA_SAFETY_INT_STATUS		0x00001080
+#define MSUIS				BIT(29)
+#define MSCIS				BIT(28)
+#define DEUIS				BIT(1)
+#define DECIS				BIT(0)
+#define DMA_ECC_INT_ENABLE		0x00001084
+#define TCEIE				BIT(0)
+#define DMA_ECC_INT_STATUS		0x00001088
+
+int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp); 
+bool dwmac5_safety_feat_irq_status(struct net_device *ndev,
+	void __iomem *ioaddr, unsigned int asp);
+
+#endif /* __DWMAC5_H__ */
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index c84c24f..97ab4ca 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -205,6 +205,7 @@ static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 
 static void stmmac_global_err(struct stmmac_priv *priv)  {
+	netif_carrier_off(priv->dev);
 	set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 	stmmac_service_event_schedule(priv);
 }
@@ -2006,6 +2007,22 @@ static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
 	}
 }
 
+static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) {
+	bool ret = false;
+
+	/* Safety features are only available in cores >= 5.10 */
+	if (priv->synopsys_id < DWMAC_CORE_5_10)
+		return ret;
+	if (priv->hw->mac->safety_feat_irq_status)
+		ret = priv->hw->mac->safety_feat_irq_status(priv->dev,
+				priv->ioaddr, priv->dma_cap.asp);
+
+	if (ret)
+		stmmac_global_err(priv);
+	return ret;
+}
+
 /**
  * stmmac_dma_interrupt - DMA ISR
  * @priv: driver private structure
@@ -2495,6 +2512,17 @@ static void stmmac_mtl_configuration(struct stmmac_priv *priv)
 		stmmac_mac_config_rx_queues_routing(priv);
 }
 
+static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 
+{
+	if (priv->hw->mac->safety_feat_config && priv->dma_cap.asp) {
+		netdev_info(priv->dev, "Enabling Safety Features\n");
+		priv->hw->mac->safety_feat_config(priv->ioaddr,
+				priv->dma_cap.asp);
+	} else {
+		netdev_info(priv->dev, "No Safety Features support found\n");
+	}
+}
+
 /**
  * stmmac_hw_setup - setup mac in a usable state.
  *  @dev : pointer to the device structure.
@@ -2546,6 +2574,10 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
 	if (priv->synopsys_id >= DWMAC_CORE_4_00)
 		stmmac_mtl_configuration(priv);
 
+	/* Initialize Safety Features */
+	if (priv->synopsys_id >= DWMAC_CORE_5_10)
+		stmmac_safety_feat_configuration(priv);
+
 	ret = priv->hw->mac->rx_ipc(priv->hw);
 	if (!ret) {
 		netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); @@ -3713,6 +3745,9 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
 	/* Check if adapter is up */
 	if (test_bit(STMMAC_DOWN, &priv->state))
 		return IRQ_HANDLED;
+	/* Check if a fatal error happened */
+	if (stmmac_safety_feat_interrupt(priv))
+		return IRQ_HANDLED;
 
 	/* To handle GMAC own interrupts */
 	if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
--
1.7.1

Powered by blists - more mailing lists