netdev - Re: [NetDev-info] Distributed Switch Architecture for 88E6390

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Message-ID: <CAOsVQT6W4Y_vx33t-JL_tvXMK+3kVHbgGMsS4YWuauGB_0ay5A@mail.gmail.com>
Date:   Mon, 5 Feb 2018 14:59:48 -0500
From:   "S.Y. Park" <sypeattle@...il.com>
To:     David Thompson <dthompson@...vision.com>, netdev@...r.kernel.org
Cc:     Miguel Calero Raventós <info@...devconf.org>,
        David Miller <davem@...emloft.net>
Subject: Re: [NetDev-info] Distributed Switch Architecture for 88E6390

Dear Mr. Thompson,

I'm forwarding to you to the technical discussion mailing list called
"netdev@...r.kernel.org".

info@...devconf.org is for discussions regarding The NetDev Society's
NetDev Conference  attendance & participation questions & concerns,
not technical discussion.

Good luck w/ your 88E6390 driver functionality testing contribution,
and I'm sure someone from the netdev mailing list can address your
question.

Sincerely,

Soyoung Park
Executive Director
The NetDev Society

On Mon, Feb 5, 2018 at 1:09 PM, David Thompson <dthompson@...vision.com> wrote:
> Hello,
>
> I am looking for contacts to anyone that is currently working on the Marvell
> 88E6390 port within the Distributed Switch Architecture.  I am working
> through a back port to 4.4.38 in a non-trivial integration and have found a
> number of issues I believe are legitimate issues that I would like to
> feedback.  I am also seeing a potential issue with outgoing TCP traffic and
> was looking to see if this is a known issue or has been investigated prior.
> I would be very happy to assist in testing the 88E6390 driver functionality.
>
> Details follow:
>
> For my configuration the CPU port is port 6, there is only one 88E6390 and
> finally port 0 and the SERDES are not used.  I am also using the GPIO
> bitbang driver for MDIO to the 88E6390 (I've confirmed that it works
> independently).
>
> First, I've noticed a few interesting discrepancies in setup and the
> datasheet for the 88E6390.  They are as follows:
>
> CPU Port port control configuration (port 0x6 reg 0x4) is configured 0x3107.
> This indicates
>
> 15:14 SA Filter Disabled
>     9:8 Frame Mode DSA
> 13:12 Egress Mode - is then in an undefined state.  According the datasheet
> it must be set to 00.
>
> Global1 Global Control 2 (addr 0x1b reg 0x1c) is configured 0xf000.  Bits
> 15:14 only supports 0x0, 0x1, and 0x2 while bits 13:12 are reserved.
> Global1 registers 0x10 -> 0x18 are written 0x0000, 0x0000, 0x5555, 0x5555,
> 0xaaaa, 0xaaaa, 0xffff, and 0xffff.  According the 88E6390 datasheet
> 0x10->0x18 are reserved.
>
>
> When I got the back-port compiling and flashed on my target device I was
> able to bring up individual ports (the phy would come up and auto-negotiate
> successfully) but could not send or receive ICMP echo/reply.  Making the
> changes associated with 1) above to be in accordance with the Marvell
> datasheet got me to a point where I could send and receive pings.
>
> I now face an interesting problem, I am currently unable to setup or
> maintain a TCP session.  Doing a wireshark capture on my host pc to the
> target device (including the 88E6390) with the appropriate port enabled I am
> seeing packet re-transmission issues from the target device.  For example,
> if I try to initiate from my host pc I will send a SYN packet and receive
> multiple identical  SYN,ACK packets returned or if I initiate from the
> target device I see multiple identical SYN packets sent.  I was wondering if
> you had ever seen this anything like this issue and if so had any
> suggestions with regards to what might be the cause?
>
> Much appreciated,
>
> Dave Thompson
>
> David Thompson BSc, MSc
> Chief Systems Architect
> Miovision
> dthompson@...vision.com
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