netdev - [PATCH v7 33/37] dt-bindings: nds32 L2 cache controller Bindings

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Message-Id: <98f2057a0a26cfba1220386ebb9a0c389ac9c95b.1518505384.git.greentime@andestech.com>
Date:   Tue, 13 Feb 2018 17:09:37 +0800
From:   Greentime Hu <green.hu@...il.com>
To:     greentime@...estech.com, linux-kernel@...r.kernel.org,
        arnd@...db.de, linux-arch@...r.kernel.org, tglx@...utronix.de,
        jason@...edaemon.net, marc.zyngier@....com, robh+dt@...nel.org,
        netdev@...r.kernel.org, deanbo422@...il.com,
        devicetree@...r.kernel.org, viro@...iv.linux.org.uk,
        dhowells@...hat.com, will.deacon@....com,
        daniel.lezcano@...aro.org, linux-serial@...r.kernel.org,
        geert.uytterhoeven@...il.com, linus.walleij@...aro.org,
        mark.rutland@....com, greg@...ah.com, ren_guo@...ky.com,
        rdunlap@...radead.org, davem@...emloft.net, jonas@...thpole.se,
        stefan.kristiansson@...nalahti.fi, shorne@...il.com
Cc:     green.hu@...il.com
Subject: [PATCH v7 33/37] dt-bindings: nds32 L2 cache controller Bindings

This patch adds nds32 L2 cache controller binding documents.

Signed-off-by: Greentime Hu <greentime@...estech.com>
Reviewed-by: Rob Herring <robh@...nel.org>
Acked-by: Arnd Bergmann <arnd@...db.de>
---
 Documentation/devicetree/bindings/nds32/atl2c.txt | 28 +++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/atl2c.txt

diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt b/Documentation/devicetree/bindings/nds32/atl2c.txt
new file mode 100644
index 000000000000..da8ab8e7ae9b
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/atl2c.txt
@@ -0,0 +1,28 @@
+* Andestech L2 cache Controller
+
+The level-2 cache controller plays an important role in reducing memory latency
+for high performance systems, such as thoese designs with AndesCore processors.
+Level-2 cache controller in general enhances overall system performance
+signigicantly and the system power consumption might be reduced as well by
+reducing DRAM accesses.
+
+This binding specifies what properties must be available in the device tree
+representation of an Andestech L2 cache controller.
+
+Required properties:
+	- compatible:
+		Usage: required
+		Value type: <string>
+		Definition: "andestech,atl2c"
+	- reg : Physical base address and size of cache controller's memory mapped
+	- cache-unified : Specifies the cache is a unified cache.
+	- cache-level : Should be set to 2 for a level 2 cache.
+
+* Example
+
+	cache-controller@...00000 {
+		compatible = "andestech,atl2c";
+		reg = <0xe0500000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
+	};
-- 
2.16.1