netdev - Re: [PATCH net-next 2/4] net: stmmac: use correct barrier between coherent memory and MMIO

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Message-Id: <20180302.095411.1270630534912987342.davem@davemloft.net>
Date:   Fri, 02 Mar 2018 09:54:11 -0500 (EST)
From:   David Miller <davem@...emloft.net>
To:     pavel@....cz
Cc:     niklas.cassel@...s.com, peppe.cavallaro@...com,
        alexandre.torgue@...com, Jose.Abreu@...opsys.com, niklass@...s.com,
        netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next 2/4] net: stmmac: use correct barrier between
 coherent memory and MMIO

From: Pavel Machek <pavel@....cz>
Date: Fri, 2 Mar 2018 10:20:00 +0100

>> This barrier cannot be a simple dma_wmb(), since a dma_wmb() is only
>> used to guarantee the ordering, with respect to other writes,
>> to cache coherent DMA memory.
> 
> Could you explain this a bit more (and perhaps in code comment)?
> 
> Ensuring other writes are done before writing the "GO!" bit should be
> enough, no?

Indeed, the chip should never look at the descriptor contents unless
the GO bit is set.

If there are ways that it can, this must be explained and documented
since it is quite unusual compared to other hardware.

> (If it is not, do we need heavier barriers in other places, too?)

Right.