netdev - Re: [PATCH net-next 2/4] net: stmmac: use correct barrier between coherent memory and MMIO

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Message-Id: <20180307.103226.1538176953286317879.davem@davemloft.net>
Date:   Wed, 07 Mar 2018 10:32:26 -0500 (EST)
From:   David Miller <davem@...emloft.net>
To:     niklas.cassel@...s.com
Cc:     pavel@....cz, peppe.cavallaro@...com, alexandre.torgue@...com,
        Jose.Abreu@...opsys.com, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next 2/4] net: stmmac: use correct barrier between
 coherent memory and MMIO

From: Niklas Cassel <niklas.cassel@...s.com>
Date: Sat, 3 Mar 2018 00:28:53 +0100

> However, the last write we do is "DMA start transmission",
> this is a register in the IP, i.e. it is a write to the cache
> incoherent MMIO region (rather than a write to cache coherent memory).
> To ensure that all writes to cache coherent memory have
> completed before we start the DMA, we have to use the barrier
> wmb() (which performs a more extensive flush compared to
> dma_wmb()).

The is an implicit memory barrier between physical memory writes
and those to MMIO register space.

So as long as you place the dma_wmb() to ensure the correct
ordering within the descriptor words, you need nothing else
after the last descriptor word write.