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Message-ID: <b02cc752d90c5e5ae2cc8cc4f67429a7@codeaurora.org>
Date: Wed, 28 Mar 2018 07:41:16 -0400
From: okaya@...eaurora.org
To: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Benjamin Herrenschmidt <benh@...nel.crashing.org>,
Alexander Duyck <alexander.duyck@...il.com>,
Will Deacon <will.deacon@....com>,
Arnd Bergmann <arnd@...db.de>, Jason Gunthorpe <jgg@...pe.ca>,
David Laight <David.Laight@...lab.com>,
Oliver <oohall@...il.com>,
"open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)"
<linuxppc-dev@...ts.ozlabs.org>, linux-rdma@...r.kernel.org,
Alexander Duyck <alexander.h.duyck@...hat.com>,
"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
netdev@...r.kernel.org, linus971@...il.com
Subject: Re: RFC on writel and writel_relaxed
On 2018-03-28 02:14, Linus Torvalds wrote:
> On Tue, Mar 27, 2018 at 5:24 PM, Sinan Kaya <okaya@...eaurora.org>
> wrote:
>>
>> Basically changing it to
>>
>> dma_buffer->foo = 1; /* WB */
>> wmb()
>> writel_relaxed(KICK, DMA_KICK_REGISTER); /* UC */
>> mmiowb()
>
> Why?
>
> Why not just remove the wmb(), and keep the barrier in the writel()?
Yes, we want to get there indeed. It is because of some arch not
implementing writel properly. Maintainers want to play safe.
That is why I asked if IA64 and other well known archs follow the
strongly ordered rule at this moment like PPC and ARM.
Or should we go and inform every arch about this before yanking wmb()?
Maintainers are afraid of introducing a regression.
>
> The above code makes no sense, and just looks stupid to me. It also
> generates pointlessly bad code on x86, so it's bad there too.
>
> Linus
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