netdev - Re: [PATCH] can: hi311x: Work around TX complete interrupt erratum

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Message-ID: <CACrMeVBSZZetJ6nzwxwqgNO2QEbdX0R-2whnCK6-bJr-5ibiuA@mail.gmail.com>
Date:   Thu, 10 May 2018 12:23:58 -0400
From:   Akshay Bhat <akshay.bhat@...esys.com>
To:     Lukas Wunner <lukas@...ner.de>
Cc:     Marc Kleine-Budde <mkl@...gutronix.de>,
        Wolfgang Grandegger <wg@...ndegger.com>,
        linux-can@...r.kernel.org, netdev@...r.kernel.org,
        Mathias Duckeck <m.duckeck@...bus.de>,
        Casey Fitzpatrick <casey.fitzpatrick@...esys.com>
Subject: Re: [PATCH] can: hi311x: Work around TX complete interrupt erratum

On Wed, May 9, 2018 at 8:43 AM, Lukas Wunner <lukas@...ner.de> wrote:
> When sending packets as fast as possible using "cangen -g 0 -i -x", the
> HI-3110 occasionally latches the interrupt pin high on completion of a
> packet, but doesn't set the TXCPLT bit in the INTF register.  The INTF
> register contains 0x00 as if no interrupt has occurred.  Even waiting
> for a few milliseconds after the interrupt doesn't help.
>
> Work around this apparent erratum by instead checking the TXMTY bit in
> the STATF register ("TX FIFO empty").  We know that we've queued up a
> packet for transmission if priv->tx_len is nonzero.  If the TX FIFO is
> empty, transmission of that packet must have completed.
>
> Note that this is congruent with our handling of received packets, which
> likewise gleans from the STATF register whether a packet is waiting in
> the RX FIFO, instead of looking at the INTF register.
>
> Cc: Mathias Duckeck <m.duckeck@...bus.de>
> Cc: Akshay Bhat <akshay.bhat@...esys.com>
> Cc: Casey Fitzpatrick <casey.fitzpatrick@...esys.com>
> Cc: stable@...r.kernel.org # v4.12+
> Signed-off-by: Lukas Wunner <lukas@...ner.de>
> ---

Acked-by: Akshay Bhat <akshay.bhat@...esys.com>