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Message-Id: <20180518.135518.1523464125252752428.davem@davemloft.net>
Date: Fri, 18 May 2018 13:55:18 -0400 (EDT)
From: David Miller <davem@...emloft.net>
To: rahul.lakkireddy@...lsio.com
Cc: netdev@...r.kernel.org, ganeshgr@...lsio.com,
nirranjan@...lsio.com, indranil@...lsio.com
Subject: Re: [PATCH net] cxgb4: fix offset in collecting TX rate limit info
From: Rahul Lakkireddy <rahul.lakkireddy@...lsio.com>
Date: Fri, 18 May 2018 19:13:37 +0530
> Correct the indirect register offsets in collecting TX rate limit info
> in UP CIM logs.
>
> Also, T5 doesn't support these indirect register offsets, so remove
> them from collection logic.
>
> Fixes: be6e36d916b1 ("cxgb4: collect TX rate limit info in UP CIM logs")
> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@...lsio.com>
> Signed-off-by: Ganesh Goudar <ganeshgr@...lsio.com>
Applied and queued up for -stable, thanks.
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