netdev - Re: [PATCH 0/4 RFCv2] Realtek SMI RTL836x DSA driver

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Message-ID: <CACRpkdbem_jTe6cQwTeTi9Uhk2B88rGENePZvjbsq38mfvcs0A@mail.gmail.com>
Date:   Tue, 29 May 2018 20:41:49 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Vivien Didelot <vivien.didelot@...oirfairelinux.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        netdev <netdev@...r.kernel.org>,
        OpenWrt Development List <openwrt-devel@...ts.openwrt.org>,
        LEDE Development List <lede-dev@...ts.infradead.org>
Subject: Re: [PATCH 0/4 RFCv2] Realtek SMI RTL836x DSA driver

On Tue, May 29, 2018 at 2:24 PM, Andrew Lunn <andrew@...n.ch> wrote:

> Did you look at the switch end? I found a datasheet for the
> 8366/8369. Register at 0x0050, P8GCR. It has two bits for RGMII
> delays.

Unfortunately this datasheet is not applicable to RTL8366RB.

RTL documentation and model numbers are a complete mess
around the time when this chip came out, unfortunately... I even
started to implement using that datasheet and had to toss a bunch
of stuff away.

There might not even be a proper datasheet for RTL8366RB,
I'm afraid. The best we have is different (3 different AFAICT)
vendor code drops. Here is one drop over at DD-WRT:
https://svn.dd-wrt.com//browser/src/linux/universal/linux-3.2/drivers/net/ethernet/raeth/rb

As you can see, the RTL8366RB vendor driver consists of
a hacked version of their RTL8368S driver, so apparently those
two ASICs are similar, they even kept the same filenames.

For example the register defintions:
https://svn.dd-wrt.com/browser/src/linux/universal/linux-3.2/drivers/net/ethernet/raeth/rb/rtl8368s_reg.h

> With RGMII delays, you have 3 'choices'.
>
> 1) The hardware design includes the delay, by zig-zagging the clock
> line to make it longer.
> 2) The 'MAC' side does the delay.
> 3) The 'PHY' side does the delay.
>
> I normally recommend the PHY side doing it, because that's what most
> board do. Gives us some consistency. But it does not really
> matter. Just make sure one side, and only once side is inserting the
> delays.

Makes sense! But I haven't found anything applicable in the
RTL8366RB registers.

There are some jam tables with magic values written all over
the place that have no documentation, I fear this is one of the
settings poked around with there.

However, even if this router did not come with any code for
the RTL8366RB driver, I disassembled the binary to verify
that they use the same magic jam table, so the ASIC is
initialized in the same way.

Yours,
Linus Walleij