netdev - Re: [OpenWrt-Devel] [PATCH 0/4 RFCv2] Realtek SMI RTL836x DSA driver

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Message-ID: <6FB2D569-87D4-47A9-AB6D-51B85720B6DA@darbyshire-bryant.me.uk>
Date:   Tue, 29 May 2018 18:57:42 +0000
From:   Kevin Darbyshire-Bryant <kevin@...byshire-bryant.me.uk>
To:     Linus Walleij <linus.walleij@...aro.org>
CC:     Andrew Lunn <andrew@...n.ch>, netdev <netdev@...r.kernel.org>,
        Florian Fainelli <f.fainelli@...il.com>,
        LEDE Development List <openwrt-devel@...ts.openwrt.org>,
        Vivien Didelot <vivien.didelot@...oirfairelinux.com>
Subject: Re: [OpenWrt-Devel] [PATCH 0/4 RFCv2] Realtek SMI RTL836x DSA driver



> On 29 May 2018, at 19:41, Linus Walleij <linus.walleij@...aro.org> wrote:
> 
> On Tue, May 29, 2018 at 2:24 PM, Andrew Lunn <andrew@...n.ch> wrote:
> 
>> Did you look at the switch end? I found a datasheet for the
>> 8366/8369. Register at 0x0050, P8GCR. It has two bits for RGMII
>> delays.
> 
> Unfortunately this datasheet is not applicable to RTL8366RB.
> 
> RTL documentation and model numbers are a complete mess
> around the time when this chip came out, unfortunately... I even
> started to implement using that datasheet and had to toss a bunch
> of stuff away.
> 
> There might not even be a proper datasheet for RTL8366RB,
> I'm afraid. The best we have is different (3 different AFAICT)
> vendor code drops. Here is one drop over at DD-WRT:
> https://svn.dd-wrt.com//browser/src/linux/universal/linux-3.2/drivers/net/ethernet/raeth/rb
> 
> As you can see, the RTL8366RB vendor driver consists of
> a hacked version of their RTL8368S driver, so apparently those
> two ASICs are similar, they even kept the same filenames.
> 
> For example the register defintions:
> https://svn.dd-wrt.com/browser/src/linux/universal/linux-3.2/drivers/net/ethernet/raeth/rb/rtl8368s_reg.h
> 
>> With RGMII delays, you have 3 'choices'.
>> 
>> 1) The hardware design includes the delay, by zig-zagging the clock
>> line to make it longer.
>> 2) The 'MAC' side does the delay.
>> 3) The 'PHY' side does the delay.
>> 
>> I normally recommend the PHY side doing it, because that's what most
>> board do. Gives us some consistency. But it does not really
>> matter. Just make sure one side, and only once side is inserting the
>> delays.
> 
> Makes sense! But I haven't found anything applicable in the
> RTL8366RB registers.
> 
> There are some jam tables with magic values written all over
> the place that have no documentation, I fear this is one of the
> settings poked around with there.
> 
> However, even if this router did not come with any code for
> the RTL8366RB driver, I disassembled the binary to verify
> that they use the same magic jam table, so the ASIC is
> initialized in the same way.
> 
> Yours,
> Linus Walleij
> 
> _______________________________________________
> openwrt-devel mailing list
> openwrt-devel@...ts.openwrt.org
> https://lists.openwrt.org/listinfo/openwrt-devel

Oh lordy, that horrible device as exhibited in the netgear DGN3500.  Talk about magic values https://git.openwrt.org/?p=openwrt/openwrt.git;a=commit;h=42120bd7f323ff7170b32a5fd4674babd8b184bc

Cheers,

Kevin D-B

012C ACB2 28C6 C53E 9775  9123 B3A2 389B 9DE2 334A


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