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Message-ID: <20180628083530.GE16727@lunn.ch>
Date: Thu, 28 Jun 2018 10:35:30 +0200
From: Andrew Lunn <andrew@...n.ch>
To: "Steven J. Hill" <steven.hill@...ium.com>
Cc: netdev@...r.kernel.org, Carlos Munoz <cmunoz@...ium.com>,
Chandrakala Chavva <cchavva@...iumnetworks.com>
Subject: Re: [PATCH v12 01/10] dt-bindings: Add Cavium Octeon Common Ethernet
Interface.
> +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting.
> + Needed by the Micrel PHY.
Could you explain this some more. Is it anything to do with RGMII delays?
Thanks
Andrew
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