netdev - [PATCH net 2/2] tg3: Add higher cpu clock for 5762.

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Date:   Mon, 16 Jul 2018 11:13:32 +0530
From:   Siva Reddy Kallam <siva.kallam@...adom.com>
To:     davem@...emloft.net
Cc:     netdev@...r.kernel.org, michael.chan@...adcom.com,
        prashant.sreedharan@...adcom.com, sanjeevb.bansal@...adcom.com,
        Siva Reddy Kallam <siva.kallam@...adcom.com>
Subject: [PATCH net 2/2] tg3: Add higher cpu clock for 5762.

From: Sanjeev Bansal <sanjeevb.bansal@...adcom.com>

This patch has fix for TX timeout while running bi-directional
traffic with 100 Mbps using 5762.

Signed-off-by: Sanjeev Bansal <sanjeevb.bansal@...adcom.com>
Signed-off-by: Siva Reddy Kallam <siva.kallam@...adcom.com>
Reviewed-by: Michael Chan <michael.chan@...adcom.com>
---
 drivers/net/ethernet/broadcom/tg3.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 2ee1527..aa1374d 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -9294,6 +9294,15 @@ static int tg3_chip_reset(struct tg3 *tp)
 
 	tg3_restore_clk(tp);
 
+	/* Increase the core clock speed to fix tx timeout issue for 5762
+	 * with 100Mbps link speed.
+	 */
+	if (tg3_asic_rev(tp) == ASIC_REV_5762) {
+		val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
+		tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
+		     TG3_CPMU_MAC_ORIDE_ENABLE);
+	}
+
 	/* Reprobe ASF enable state.  */
 	tg3_flag_clear(tp, ENABLE_ASF);
 	tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
-- 
1.8.3.1