netdev - [PATCH net-next 0/3] mlxsw: Enable MC-aware mode for mlxsw ports

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Message-Id: <20180805060308.7862-1-idosch@mellanox.com>
Date:   Sun,  5 Aug 2018 09:03:05 +0300
From:   Ido Schimmel <idosch@...lanox.com>
To:     netdev@...r.kernel.org
Cc:     davem@...emloft.net, jiri@...lanox.com, petrm@...lanox.com,
        mlxsw@...lanox.com, Ido Schimmel <idosch@...lanox.com>
Subject: [PATCH net-next 0/3] mlxsw: Enable MC-aware mode for mlxsw ports

Petr says:

Due to an issue in Spectrum chips, when unicast traffic shares the same
queue as BUM traffic, and there is a congestion, the BUM traffic is
admitted to the queue anyway, thus pushing out all UC traffic. In order
to give unicast traffic precedence over BUM traffic, configure
multicast-aware mode on all ports.

Under multicast-aware regime, when assigning traffic class to a packet,
the switch doesn't merely take the value prescribed by the QTCT
register. For BUM traffic, it instead assigns that value plus 8. That
limits the number of available TCs, but since mlxsw currently only uses
the lower eight anyway, it is no real loss.

The two TCs (UC and MC one) are then mapped to the same subgroup and
strictly prioritized so that UC traffic is preferred in case of
congestion.

In patch #1, introduce a new register, QTCTM, which enables the
multicast-aware mode.

In patch #2, fix a typo in related code.

In patch #3, set up TCs and QTCTM to enable multicast-aware mode.

Petr Machata (3):
  mlxsw: reg: Add QoS Switch Traffic Class Table is Multicast-Aware
    Register
  mlxsw: spectrum: Fix a typo
  mlxsw: spectrum: Configure MC-aware mode on mlxsw ports

 drivers/net/ethernet/mellanox/mlxsw/reg.h     | 37 +++++++++++++++++++
 .../net/ethernet/mellanox/mlxsw/spectrum.c    | 29 ++++++++++++++-
 2 files changed, 65 insertions(+), 1 deletion(-)

-- 
2.17.1