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Message-ID: <CAAtXAHceYgPx4A7F14AYEQs9RFo2hP6JTkApHa_GtbxVcdiQNA@mail.gmail.com> Date: Thu, 30 Aug 2018 09:39:39 -0700 From: Moritz Fischer <moritz.fischer@...us.com> To: Andrew Lunn <andrew@...n.ch> Cc: "David S. Miller" <davem@...emloft.net>, Kees Cook <keescook@...omium.org>, Florian Fainelli <f.fainelli@...il.com>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, netdev@...r.kernel.org, Alex Williams <alex.williams@...com> Subject: Re: [PATCH net-next 2/3] net: nixge: Add support for having nixge as subdevice Hi Andrew, On Wed, Aug 29, 2018 at 8:11 PM, Andrew Lunn <andrew@...n.ch> wrote: > Could you tell us more about the parent device. I'm guessing PCIe. Is > it x86 so no device tree? Are there cases where it does not have a PHY > connected? What is connected instead? SFP? A switch? Can there be > multiple PHYs on the MDIO bus? The device is part of a larger FPGA design. One use case that I was trying to support with this patch is PCIe with x86 (hopefully on it's own PF...) Since the whole design isn't completely done, these are the use cases I see upcoming and current: ARM(64): a) DT: PHY over MDIO (current use case), fixed-link with GPIO (coming) b) DT: SFP (potentially coming) x86: a) no PHY (coming)-> fixed-link with GPIO b) SFP (potentially), PHY over MDIO (potentially) Thanks for your help, Moritz
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