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Message-ID: <cd2f572a-9c1f-41c1-6e95-759cfec501d9@rockbox.org>
Date: Sat, 8 Sep 2018 13:05:11 +0200
From: Thomas Martitz <kugel@...kbox.org>
To: Peter Wu <peter@...ensteyn.nl>, Daniel Drake <drake@...lessm.com>
Cc: bhelgaas@...gle.com, linux-pci@...r.kernel.org, linux@...lessm.com,
nouveau@...ts.freedesktop.org, linux-pm@...r.kernel.org,
kherbst@...hat.com, andriy.shevchenko@...ux.intel.com,
rafael.j.wysocki@...el.com, keith.busch@...el.com,
mika.westerberg@...ux.intel.com, jonathan.derrick@...el.com,
davem@...emloft.net, hkallweit1@...il.com, netdev@...r.kernel.org,
nic_swsd@...ltek.com
Subject: Re: [PATCH] PCI: Reprogram bridge prefetch registers on resume
Am 07.09.18 um 17:05 schrieb Peter Wu:
> On Fri, Sep 07, 2018 at 01:36:14PM +0800, Daniel Drake wrote:
> <..>
>> Thomas Martitz reports that this workaround also solves an issue where
>> the AMD Radeon Polaris 10 GPU on the HP Zbook 14u G5 is unresponsive
>> after S3 suspend/resume.
>
> Where was this claimed? It is not stated in the linked bug:
> (https://bugs.freedesktop.org/show_bug.cgi?id=105760
>
Actually, I reported that https://patchwork.kernel.org/patch/10583229/
works. I updated the bug now, I didn't do so yet because it's closed.
However, I did not actually test the exact patch *this* thread is about.
Do you want me to give it a spin?
Best regards.
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