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Message-ID: <20181023164832.GB12019@localhost>
Date: Tue, 23 Oct 2018 18:48:32 +0200
From: Miroslav Lichvar <mlichvar@...hat.com>
To: "Keller, Jacob E" <jacob.e.keller@...el.com>
Cc: "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
Richard Cochran <richardcochran@...il.com>
Subject: Re: Improving accuracy of PHC readings
On Fri, Oct 19, 2018 at 04:52:13PM +0000, Keller, Jacob E wrote:
> > This should significantly improve the accuracy of the synchronization,
> > reduce the uncertainty in the readings to less than a half or third,
> > and also reduce the jitter as there are fewer register reads sensitive
> > to the PCIe delay.
> >
> > What do you think?
> >
>
> Nice! I think this is good. I'd love to see some data to back it up, but it makes sense to me.
I tried a quick hack with an X550 and I219. The delay dropped from
about 2940 ns to 1040 ns on the first port of the X550, from 1920 ns
to 660 ns on the second port of the X550, and from 2500 ns to 1300 ns
on the I219.
The I219 supports the SYS_OFFSET_PRECISE ioctl (cross timestamping),
which we can use for comparison. The difference between the offsets
calculated using the two ioctls was about 500-600 ns before and now it
is about -50--150 ns.
I was not able to find any information on how accurate cross
timestamping on this HW is actually supposed to be, so I'm wondering
which of the two is closer to the truth.
Here is an output from phc2sys with the I219:
Before:
phc offset -59 s2 freq +40 delay 2527
phc offset 19 s2 freq +101 delay 2526
phc offset -23 s2 freq +64 delay 2522
phc offset 46 s2 freq +126 delay 2535
phc offset -32 s2 freq +62 delay 2530
phc offset -10 s2 freq +75 delay 2526
phc offset 102 s2 freq +184 delay 2523
After:
phc offset 17 s2 freq +105 delay 1298
phc offset 47 s2 freq +140 delay 1299
phc offset -42 s2 freq +65 delay 1293
phc offset -6 s2 freq +88 delay 1299
phc offset 34 s2 freq +127 delay 1300
phc offset -14 s2 freq +89 delay 1301
phc offset -86 s2 freq +13 delay 1296
phc offset -21 s2 freq +52 delay 1298
--
Miroslav Lichvar
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