netdev - Re: [PATCH v2 0/7] IP101GR: devicetree based configuration of SEL

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-Id: <20181118.161640.141528330634887893.davem@davemloft.net>
Date:   Sun, 18 Nov 2018 16:16:40 -0800 (PST)
From:   David Miller <davem@...emloft.net>
To:     martin.blumenstingl@...glemail.com
Cc:     netdev@...r.kernel.org, devicetree@...r.kernel.org,
        f.fainelli@...il.com, andrew@...n.ch, mark.rutland@....com,
        robh+dt@...nel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 0/7] IP101GR: devicetree based configuration of
 SEL_INTR32

From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Date: Sun, 18 Nov 2018 22:23:52 +0100

> The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA
> Ethernet PHY. Due to it's limited amount of pins the RXER (receive
> error) and INTR32 (interrupt) functions share pin 21.
 ...

Series applied to net-next, thank you.