netdev - Re: [PATCH 2/2] arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal

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Date:   Fri, 30 Nov 2018 18:45:35 +0100
From:   Gregory CLEMENT <gregory.clement@...tlin.com>
To:     Baruch Siach <baruch@...s.co.il>
Cc:     Jason Cooper <jason@...edaemon.net>, Andrew Lunn <andrew@...n.ch>,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        linux-arm-kernel@...ts.infradead.org,
        Russell King <linux@...linux.org.uk>,
        Ori Shemtov <ori.shemtov@...id-run.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        netdev@...r.kernel.org, Linus Walleij <linus.walleij@...aro.org>
Subject: Re: [PATCH 2/2] arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal

Hi Baruch,
 
 On mar., oct. 16 2018, Baruch Siach <baruch@...s.co.il> wrote:

> This reset signal controls the Marvell 1512 1G PHY.
>
> Note that current implementation queries the PHY over the MDIO bus
> (get_phy_device() call from of_mdiobus_register_phy()) before reset
> signal deassert. If the PHY reset signal is asserted at boot time, PHY
> registration fails. So current code relies on the bootloader to deassert
> the reset signal.

Applied on mvebu/dt64

Thanks,

Gregory

>
> Signed-off-by: Baruch Siach <baruch@...s.co.il>
> ---
>  arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> index af1310c53bc8..73df0ef5e0c4 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> @@ -337,6 +337,10 @@
>  		 */
>  		marvell,reg-init = <3 16 0 0x1017>;
>  		reg = <0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&cp0_copper_eth_phy_reset>;
> +		reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
> +		reset-assert-us = <10000>;
>  	};
>  
>  	switch0: switch0@4 {
> -- 
> 2.19.1
>

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com