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Message-Id: <1543876074-4372-1-git-send-email-jiong.wang@netronome.com>
Date:   Mon,  3 Dec 2018 17:27:54 -0500
From:   Jiong Wang <jiong.wang@...ronome.com>
To:     daniel@...earbox.net, ast@...nel.org
Cc:     netdev@...r.kernel.org, oss-drivers@...ronome.com,
        Jiong Wang <jiong.wang@...ronome.com>,
        Markos Chandras <markos.chandras@...tec.com>,
        Paul Burton <paul.burton@...s.com>, linux-mips@...r.kernel.org
Subject: [PATCH v2 bpf] mips: bpf: fix encoding bug for mm_srlv32_op

For micro-mips, srlv inside POOL32A encoding space should use 0x50
sub-opcode, NOT 0x90.

Some early version ISA doc describes the encoding as 0x90 for both srlv and
srav, this looks to me was a typo. I checked Binutils libopcode
implementation which is using 0x50 for srlv and 0x90 for srav.

v1->v2:
  - Keep mm_srlv32_op sorted by value.

Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
Cc: Markos Chandras <markos.chandras@...tec.com>
Cc: Paul Burton <paul.burton@...s.com>
Cc: linux-mips@...r.kernel.org
Acked-by: Jakub Kicinski <jakub.kicinski@...ronome.com>
Acked-by: Song Liu <songliubraving@...com>
Signed-off-by: Jiong Wang <jiong.wang@...ronome.com>
---
 arch/mips/include/uapi/asm/inst.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index c05dcf5..273ef58 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -369,8 +369,8 @@ enum mm_32a_minor_op {
 	mm_ext_op = 0x02c,
 	mm_pool32axf_op = 0x03c,
 	mm_srl32_op = 0x040,
+	mm_srlv32_op = 0x050,
 	mm_sra_op = 0x080,
-	mm_srlv32_op = 0x090,
 	mm_rotr_op = 0x0c0,
 	mm_lwxs_op = 0x118,
 	mm_addu32_op = 0x150,
-- 
2.7.4

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