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Message-Id: <20181204.121005.571815746293422434.davem@davemloft.net>
Date:   Tue, 04 Dec 2018 12:10:05 -0800 (PST)
From:   David Miller <davem@...emloft.net>
To:     alexei.starovoitov@...il.com
Cc:     jiong.wang@...ronome.com, daniel@...earbox.net, ast@...nel.org,
        netdev@...r.kernel.org, oss-drivers@...ronome.com
Subject: Re: [RFC bpf-next 1/7] bpf: interpreter support BPF_ALU | BPF_ARSH

From: Alexei Starovoitov <alexei.starovoitov@...il.com>
Date: Tue, 4 Dec 2018 11:29:55 -0800

> I guess sparc doesn't really have 32 subregisters.  All registers
> are considered 64-bit. It has 32-bit alu ops on 64-bit registers
> instead.

Right.

Anyways, sparc will require two instructions because of this, the
'sra' then a 'srl' by zero bits to clear the top 32-bits.

I'll code up the sparc JIT part when this goes in.

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