lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 9 Jan 2019 22:56:28 +0100
From:   Marek Vasut <marex@...x.de>
To:     Tristram.Ha@...rochip.com
Cc:     f.fainelli@...il.com, andrew@...n.ch, Woojung.Huh@...rochip.com,
        netdev@...r.kernel.org, UNGLinuxDriver@...rochip.com
Subject: Re: [RFT][PATCH V2 09/10] net: dsa: microchip: Factor out regmap
 config generation into common header

On 1/9/19 8:08 PM, Tristram.Ha@...rochip.com wrote:
>>>>> +	{								\
>>>>> +		.val_bits = (width),					\
>>>>> +		.reg_stride = (width) / 8,				\
>>>>> +		.reg_bits = (regbits) + (regalign),			\
>>>>> +		.pad_bits = (regpad),					\
>>>>> +		.max_register = 0xF00,					\
>>>>> +		.cache_type = REGCACHE_NONE,
>>>>> 	\
>>>>> +		.read_flag_mask =					\
>>>>> +			KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, regbits,
>>>>> regpad), \
>>>>> +		.write_flag_mask =					\
>>>>> +			KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, regbits,
>>>>> regpad), \
>>>>> +		.reg_format_endian = REGMAP_ENDIAN_BIG,
>>>>> 	\
>>>>> +		.val_format_endian = REGMAP_ENDIAN_BIG
>>>>> 	\
>>>>> +	}
>>>>
>>>> max_registers for KSZ9477 should be 0x8000.
>>>>
>>>> I found that the SPI access works with these settings:
>>>> reg_bits = 32 - 5, val_bits = 8, pad_bits = 5, read_flag_mask =
>> KS_SPIOP_RD << 5.
>>>
>>> This is wrong, val_bits must match the register width (8 for 8bit
>>> regmap, 16 for 16bit regmap etc). Anyway, can you prepare a short diff
>>> to give me an idea what needs to be changed ?
>>>
>>
>> Bump ?
>>
> 
> This is the regmap_config I used in Linux 4.9:
> 
> 	.reg_bits		= SPI_REGMAP_REG,
> 	.val_bits		= SPI_REGMAP_VAL,
> 	.pad_bits		= SPI_REGMAP_PAD,
> 	.read_flag_mask	= KS_SPIOP_RD << SPI_REGMAP_MASK_S,
> 	.write_flag_mask	= KS_SPIOP_WR << SPI_REGMAP_MASK_S,
> 	.reg_format_endian	= REGMAP_ENDIAN_BIG,
> 	.val_format_endian	= REGMAP_ENDIAN_BIG,
> 
> For KSZ9477:
> 
> SPI_CMD_LEN		4
> SPI_REGMAP_PAD	SPI_TURNAROUND_SHIFT
> SPI_REGMAP_VAL	8
> SPI_REGMAP_REG	\
> 	(SPI_CMD_LEN * SPI_REGMAP_VAL - SPI_TURNAROUND_SHIFT)
> SPI_REGMAP_MASK_S	\
> 	(SPI_ADDR_SHIFT + SPI_TURNAROUND_SHIFT - \
> 	(SPI_CMD_LEN * SPI_REGMAP_VAL - 8))
> 
> For KSZ8795:
> 
> SPI_CMD_LEN		2
> SPI_REGMAP_PAD	SPI_TURNAROUND_S
> SPI_REGMAP_VAL	8
> SPI_REGMAP_REG	\
> 	(SPI_CMD_LEN * SPI_REGMAP_VAL - SPI_TURNAROUND_S)
> SPI_REGMAP_MASK_S	\
> 	(SPI_ADDR_S + SPI_TURNAROUND_S - \
> 	(SPI_CMD_LEN * SPI_REGMAP_VAL - 8))
> 
> So the differences between KSZ9477 and KSZ8795 are SPI_CMD_LEN, SPI_ADDR_S, and SPI_TURNAROUND_S.
> 
> KSZ9477:
> 
> .reg_bits = 32 - 5 = 27
> .val_bits = 8
> .pad_bits = 5
> .read_flag_mask = KS_SPIOP_RD << 5,
> 
> KSZ8795:
> 
> .reg_bits = 16 - 1 = 15
> .val_bits = 8
> .pad_bits = 1
> .read_flag_mask = KS_SPIOP_RD << 5,
> 
> The regmap.c code uses reg_bits + reg_shift (which comes from pad_bits) to decide whether the register space is 16-bit or 32-bit.  The value space is always 8-bit.
> 
> The shift for _flag_mask turns out to be the same for both KSZ9477 and KSZ8795.

Can you prepare a patch ? One which can apply on top of this series , so
we get the authorship information and stuff ?

Also, can you test this on net-next or next ?

-- 
Best regards,
Marek Vasut

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ