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Date:   Thu, 17 Jan 2019 13:05:42 +0100
From:   Simon Horman <horms@...ge.net.au>
To:     Fabrizio Castro <fabrizio.castro@...renesas.com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Wolfgang Grandegger <wg@...ndegger.com>,
        Marc Kleine-Budde <mkl@...gutronix.de>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Magnus Damm <magnus.damm@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Thierry Reding <treding@...dia.com>,
        Andreas Färber <afaerber@...e.de>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Kevin Hilman <khilman@...libre.com>,
        Johan Hovold <johan@...nel.org>,
        Lukasz Majewski <lukma@...x.de>,
        Michal Simek <monstr@...str.eu>,
        Michal Vokáč <michal.vokac@...ft.com>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        Ben Whitten <ben.whitten@...il.com>,
        Chris Paterson <Chris.Paterson2@...esas.com>,
        linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
        linux-can@...r.kernel.org, netdev@...r.kernel.org,
        linux-clk@...r.kernel.org, Biju Das <biju.das@...renesas.com>,
        ebiharaml@...linux.co.jp
Subject: Re: [PATCH 10/11] arm64: dts: renesas: r8a774c0: Add clkp2 clock to
 CAN nodes

On Wed, Jan 16, 2019 at 06:37:53PM +0000, Fabrizio Castro wrote:
> According to the latest information, clkp2 is available on RZ/G2.
> Modify CAN0 and CAN1 nodes accordingly.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@...renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@...esas.com>

Taking your word for the motivation for this change,
this patch seems fine to me but I would like to wait for review
from others.

Reviewed-by: Simon Horman <horms+renesas@...ge.net.au>

> ---
>  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> index 3970aaf..326ab3a 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> @@ -809,8 +809,10 @@
>  				     "renesas,rcar-gen3-can";
>  			reg = <0 0xe6c30000 0 0x1000>;
>  			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
> -			clock-names = "clkp1", "can_clk";
> +			clocks = <&cpg CPG_MOD 916>,
> +				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
> +				 <&can_clk>;
> +			clock-names = "clkp1", "clkp2", "can_clk";
>  			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
>  			resets = <&cpg 916>;
>  			status = "disabled";
> @@ -821,8 +823,10 @@
>  				     "renesas,rcar-gen3-can";
>  			reg = <0 0xe6c38000 0 0x1000>;
>  			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
> -			clock-names = "clkp1", "can_clk";
> +			clocks = <&cpg CPG_MOD 915>,
> +				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
> +				 <&can_clk>;
> +			clock-names = "clkp1", "clkp2", "can_clk";
>  			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
>  			resets = <&cpg 915>;
>  			status = "disabled";
> -- 
> 2.7.4
> 

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