netdev - Re: net: phylink: dsa: mv88e6xxx: flaky link detection on switch ports with internal PHYs

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Date:   Tue, 22 Jan 2019 23:36:49 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     John David Anglin <dave.anglin@...l.net>
Cc:     Russell King <linux@....linux.org.uk>,
        Vivien Didelot <vivien.didelot@...oirfairelinux.com>,
        Florian Fainelli <f.fainelli@...il.com>, netdev@...r.kernel.org
Subject: Re: net: phylink: dsa: mv88e6xxx: flaky link detection on switch
 ports with internal PHYs

On Tue, Jan 22, 2019 at 04:40:27PM -0500, John David Anglin wrote:
> Hi Andrew,
> 
> On 1/22/2019 3:28 PM, Andrew Lunn wrote:
> >Does it make a difference if you do it by hand? Bring up the master
> >interface, wan, lan0, lan1, add any bridge you need, etc.
> >
> >> From power on, none of the wan, lan0, lan1 or br0 achieve link
> >>(LOWER_UP).
> I can explore this but I don't know at the moment.  I believe that all
> interfaces are configured.

Hi John

In what order? The master interface has to be up first before any
slave interface is configured up.

> In serdes.c, interrupts are used to monitor link changes.  However, phy.c
> doesn't do this and
> it doesn't call phylink_mac_change().

It does not need to. There are two options here:

1) The PHY has no interrupt. phylib will poll the PHY once per second
   for link changes.

2) The PHY has in interrupt. Link changes will cause the interrupt to
   fire, and the phylib will then read the current state.

For PHYs embedded within a switch driver by mv88e6xxx interrupts
should always be used.

I will do some testing on my espressobin.

  Andrew