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Date:   Thu, 24 Jan 2019 14:05:44 +0900
From:   Atsushi Nemoto <atsushi.nemoto@...d.co.jp>
To:     <dalon.westergreen@...ux.intel.com>
CC:     <thor.thayer@...ux.intel.com>, <netdev@...r.kernel.org>,
        <tomonori.sakita@...d.co.jp>
Subject: Re: [PATCH] net: altera_tse: fix msgdma_tx_completion on non-zero
 fill_level case

On Wed, 23 Jan 2019 14:47:06 -0800, Dalon L Westergreen <dalon.westergreen@...ux.intel.com> wrote:
>> >   	if (inuse) { /* Tx FIFO is not empty */
>> > -		ready = priv->tx_prod - priv->tx_cons - inuse - 1;
>> > +		ready = priv->tx_prod - priv->tx_cons - inuse;
> dont think my last email went through..
> 
> I am not sure about this.  This register indicates the number of entries
> still to be processed by the dma.  the -1 is intended to represent the
> decriptor currently being processed.  If ready is 
> priv->tx_prod - priv->tx_cons - inuse couldn't you end up processing 1
> too many packets?  IE: ready is 1 greater then the actual completed
> packets?
> 
> I do agree that we should not be returning a negative value, but i dont
> think i agree removing the -1 is the answer.  perhaps just check that ready
> is greater than 0?

Thank you for review.

I agree with you.  It would be OK returning a possibly off-by-one
value unless it is not an negative value.

Then, how about this instead?

--- a/drivers/net/ethernet/altera/altera_msgdma.c
+++ b/drivers/net/ethernet/altera/altera_msgdma.c
@@ -145,7 +145,8 @@ u32 msgdma_tx_completions(struct altera_tse_private *priv)
 			& 0xffff;
 
 	if (inuse) { /* Tx FIFO is not empty */
-		ready = priv->tx_prod - priv->tx_cons - inuse - 1;
+		ready = max_t(int,
+			      priv->tx_prod - priv->tx_cons - inuse - 1, 0);
 	} else {
 		/* Check for buffered last packet */
 		status = csrrd32(priv->tx_dma_csr, msgdma_csroffs(status));
-- 

If it was OK, I will post an updated patch.

---
Atsushi Nemoto


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