netdev - Re: [PATCH] Revert "net: phy: marvell: avoid pause mode on SGMII-to-Copper for 88e151x"

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Message-ID: <20190126162303.ubc6tqkdv267pi36@e5254000004ec.dyn.armlinux.org.uk>
Date:   Sat, 26 Jan 2019 16:23:04 +0000
From:   Russell King - ARM Linux admin <linux@...linux.org.uk>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org
Subject: Re: [PATCH] Revert "net: phy: marvell: avoid pause mode on
 SGMII-to-Copper for 88e151x"

On Sat, Jan 26, 2019 at 04:58:34PM +0100, Andrew Lunn wrote:
> On Fri, Jan 25, 2019 at 11:27:57PM +0000, Russell King wrote:
> > This reverts commit 6623c0fba10ef45b64ca213ad5dec926f37fa9a0.
> > 
> > The original diagnosis was incorrect: it appears that the NIC had
> > PHY polling mode enabled, which meant that it overwrote the PHYs
> > advertisement register during negotiation.
> 
> Hi Russell
> 
> The NIC wrote to PHY registers? The NIC reading the PHY in hardware is
> bad enough, but changing register as well is not good.

Yep, it seems so.

> What NIC is this? And do you have further patches to really disable
> PHY polling?

The PP2.2 in 8040 when used with the Marvell mvpp2x driver (that I
have in my mcbin branch) - mainline's mvpp2 driver doesn't suffer
from it as that disables polling mode.

What made the diagnosis hard is that disabling phy polling by poking
the SMI registers doesn't stop the PHY being polled, it seems to need
something extra - and not having the documentation doesn't help.  As
I said, using a 'scope on the MDIO signal and noticing that the
hardware was still polling the PHY despite the poll bit disabled was
key to getting to the bottom of what was really going on.  Once I
arranged to clear it during driver initialisation and rebooted the
platform, the PHY then had the expected behaviour.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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