lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <04801425-ae14-3bfe-4eaf-2f3d552093cb@st.com> Date: Thu, 14 Feb 2019 14:48:32 +0000 From: Christophe ROULLIER <christophe.roullier@...com> To: Andrew Lunn <andrew@...n.ch> CC: "robh@...nel.org" <robh@...nel.org>, "davem@...emloft.net" <davem@...emloft.net>, "joabreu@...opsys.com" <joabreu@...opsys.com>, "mark.rutland@....com" <mark.rutland@....com>, "mcoquelin.stm32@...il.com" <mcoquelin.stm32@...il.com>, Alexandre TORGUE <alexandre.torgue@...com>, Peppe CAVALLARO <peppe.cavallaro@...com>, "linux-stm32@...md-mailman.stormreply.com" <linux-stm32@...md-mailman.stormreply.com>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "netdev@...r.kernel.org" <netdev@...r.kernel.org> Subject: Re: [PATCH 2/8] net: ethernet: stmmac: update to support all PHY config for stm32mp157c. On 2/14/19 2:40 PM, Andrew Lunn wrote: > On Thu, Feb 14, 2019 at 07:45:57AM +0100, Christophe Roullier wrote: >> @@ -131,19 +185,19 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) >> case PHY_INTERFACE_MODE_RGMII: >> val = SYSCFG_PMCR_ETH_SEL_RGMII; >> - if (dwmac->int_phyclk) >> + if (dwmac->eth_clk_sel_reg) >> val |= SYSCFG_PMCR_ETH_CLK_SEL; >> pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n"); >> break; > > Hi Christophe > > This code should handle all 4 PHY_INTERFACE_MODE_RGMII* values. > > Andrew > Hi Andrew, For RGMII we are supporting 3 modes: - normal mode (with PHY with quartz) - Phy wo crystal and phy is clocking with PLL to 25Mhz. - other mode where we used PLL from RCC (125Mhz) to clock Ethernet IP (save one pin "ETH_CK125") In driver source code I put table to sum-up all configs supported for each phy mode: + * Below table summarizes the clock requirement and clock sources for + * supported phy interface modes. + * __________________________________________________________________________ + *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125Mhz from PHY| + *| | | 25MHz | 50MHz | | + * --------------------------------------------------------------------------- + *| MII | - | eth-ck | n/a | n/a | + *| | | | | | + * --------------------------------------------------------------------------- + *| GMII | - | eth-ck | n/a | n/a | + *| | | | | | + * --------------------------------------------------------------------------- + *| RGMII | - | eth-ck | n/a | eth-ck (no pin) | + *| | | | | st,eth_clk_sel | + * --------------------------------------------------------------------------- + *| RMII | - | eth-ck | eth-ck | n/a | + *| | | | st,eth_ref_clk_sel | | + * --------------------------------------------------------------------------- Regards, Christophe
Powered by blists - more mailing lists