netdev - Re: Handling an Extra Signal at PHY Reset

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20190219133629.GN14879@lunn.ch>
Date:   Tue, 19 Feb 2019 14:36:29 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Paul Kocialkowski <paul.kocialkowski@...tlin.com>
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>, netdev@...r.kernel.org,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Mylène Josserand 
        <mylene.josserand@...tlin.com>
Subject: Re: Handling an Extra Signal at PHY Reset

On Tue, Feb 19, 2019 at 10:14:20AM +0100, Paul Kocialkowski wrote:
> Hi,
> 
> We are dealing with an Ethernet PHY (Marvell 88E1512) that comes with a
> CONFIG pin that must be connected to one of the other pins of the PHY
> to configure the LSB of the PHY address as well as I/O voltages (see
> section 2.18.1 Hardware Configuration of the datasheet). It must be
> connected "soon after reset" for the PHY to be correctly configured.
 
Hi Paul

I assume there are two PHYs on the MDIO bus, and you need to ensure
they have different addresses? Do we have an Ethernet switch involved
here, or are they two SoC Ethernet networks with one shared MDIO bus?

This seems like an odd design. I've normally seen weak pull up/down
resistors, not a switch, so i'm wondering why it is designed like
this.

   Thanks
	Andrew