netdev - Re: [PATCH] net: dsa: qca8k: Enable delay for RGMII

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Date:   Tue, 19 Feb 2019 10:29:20 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     David S Miller <davem@...emloft.net>,
        linux-arm-msm@...r.kernel.org,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        netdev@...r.kernel.org, Niklas Cassel <niklas.cassel@...aro.org>,
        Florian Fainelli <f.fainelli@...il.com>,
        Michal Vokáč <michal.vokac@...ft.com>
Subject: Re: [PATCH] net: dsa: qca8k: Enable delay for RGMII_ID mode

Hi Andrew,

On 18-02-19, 14:33, Andrew Lunn wrote:
> On Mon, Feb 18, 2019 at 06:33:51PM +0530, Vinod Koul wrote:
> > RGMII_ID specifies that we should have internal delay, so resurrect the
> > delay addition routine but under the RGMII_ID mode.
> > 
> > Fixes: 40269aa9f40a ("net: dsa: qca8k: disable delay for RGMII mode")
> > Signed-off-by: Vinod Koul <vkoul@...nel.org>
> > ---
> >  drivers/net/dsa/qca8k.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
> > index a4b6cda38016..aa1f7f1b20d3 100644
> > --- a/drivers/net/dsa/qca8k.c
> > +++ b/drivers/net/dsa/qca8k.c
> > @@ -443,6 +443,18 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
> >  		val = QCA8K_PORT_PAD_RGMII_EN;
> >  		qca8k_write(priv, reg, val);
> >  		break;
> > +	case PHY_INTERFACE_MODE_RGMII_ID:
> > +		/* RGMII_ID needs internal delay. This is enabled through
> > +		 * PORT5_PAD_CTRL for all ports, rather than individual port
> > +		 * registers
> > +		 */
> > +		qca8k_write(priv, reg,
> > +			    QCA8K_PORT_PAD_RGMII_EN |
> > +			    QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
> > +			    QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
> > +		qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
> > +			    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
> > +		break;
> 
> Hi Vinod
> 
> So i'm still confused if this is global, or per-port. The first
> register written looks to be per-port, although only for ports 0 and
> 6. The second write seems to be global.

This is still a global write which enables the delay in all the ports
(as was the case previously)

> Is there a danger that port 0 has PHY_INTERFACE_MODE_RGMII_ID and port
> 6 has PHY_INTERFACE_MODE_RGMII, and we end up with delays disabled?
> Maybe we should try to detect this, and return an error?

If that was the case, I would presume people would have reported an
issue that it doesn't work for them..?

> >  	case PHY_INTERFACE_MODE_SGMII:
> >  		qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
> >  		break;
> 
> I think it would be good to add the other two PHY_INTERFACE_MODE_RGMII
> modes to the default clause so we get an error reported that they are
> not implemented.

That is still the case:

        default:
                pr_err("xMII mode %d not supported\n", mode);
                return -EINVAL;

-- 
~Vinod