netdev - Re: Handling an Extra Signal at PHY Reset

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Message-ID: <6962f9af94b985ecb67e0386ca69ae7096f84a6e.camel@bootlin.com>
Date:   Wed, 27 Feb 2019 09:19:41 +0100
From:   Paul Kocialkowski <paul.kocialkowski@...tlin.com>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>, netdev@...r.kernel.org,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Mylène Josserand 
        <mylene.josserand@...tlin.com>
Subject: Re: Handling an Extra Signal at PHY Reset

Hi Andrew,

On Thu, 2019-02-21 at 15:04 +0100, Andrew Lunn wrote:
> > I can also confirm that it does not prevent contacting the PHY on the
> > MDIO bus, contrary to what I have stated previously.
> 
> O.K, so wrong voltage does not matter, you can still probe the PHY.
> 
> Ignore the switch. Use a pin hog to set the GPIO to the disabled
> state. And set the voltage using the PHY register during probe().

Thanks a lot for your suggestion! I have tried it out and it appears to
work just as well as before.

Although the CONFIG pin state is still sampled at PHY reset, having it
connected to the PTP clock instead of the LED pin does not seem to
change the address we're getting.

We'll stick with that solution, since it's the least invasive one.

Cheers,

Paul

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com