netdev - [PATCH] net: mscc: Enable all ports in QSGMII

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Date:   Thu, 28 Feb 2019 07:32:22 +0000
From:   <Kavyasree.Kotagiri@...rochip.com>
To:     <alexandre.belloni@...tlin.com>, <davem@...emloft.net>
CC:     <UNGLinuxDriver@...rochip.com>, <Chakri.Ponnuri@...rochip.com>,
        <netdev@...r.kernel.org>, <Kavyasree.Kotagiri@...rochip.com>,
        <Steen.Hegelund@...rochip.com>
Subject: [PATCH] net: mscc: Enable all ports in QSGMII

From: Kavya Sree Kotagiri <kavyasree.kotagiri@...rochip.com>

When Ocelot phy-mode is QSGMII, all 4 ports involved in
QSGMII shall be kept out of reset and
Tx lanes shall be enabled to pass the data.

Fixes: a556c76adc05 ("net: mscc: Add initial Ocelot switch support")
Signed-off-by: Kavya Sree Kotagiri <kavyasree.kotagiri@...rochip.com>
Signed-off-by: Steen Hegelund <Steen.Hegelund@...rochip.com>
Co-developed-by: Steen Hegelund <Steen.Hegelund@...rochip.com>
---
 drivers/net/ethernet/mscc/ocelot_board.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/mscc/ocelot_board.c b/drivers/net/ethernet/mscc/ocelot_board.c
index ca3ea2f..80d8779 100644
--- a/drivers/net/ethernet/mscc/ocelot_board.c
+++ b/drivers/net/ethernet/mscc/ocelot_board.c
@@ -267,6 +267,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
 		struct phy *serdes;
 		void __iomem *regs;
 		char res_name[8];
+		int phy_mode;
 		u32 port;
 
 		if (of_property_read_u32(portnp, "reg", &port))
@@ -292,11 +293,11 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
 		if (err)
 			return err;
 
-		err = of_get_phy_mode(portnp);
-		if (err < 0)
+		phy_mode = of_get_phy_mode(portnp);
+		if (phy_mode < 0)
 			ocelot->ports[port]->phy_mode = PHY_INTERFACE_MODE_NA;
 		else
-			ocelot->ports[port]->phy_mode = err;
+			ocelot->ports[port]->phy_mode = phy_mode;
 
 		switch (ocelot->ports[port]->phy_mode) {
 		case PHY_INTERFACE_MODE_NA:
@@ -304,6 +305,13 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
 		case PHY_INTERFACE_MODE_SGMII:
 			break;
 		case PHY_INTERFACE_MODE_QSGMII:
+			/* Ensure clock signals and speed is set on all
+			 * QSGMII links
+			 */
+			ocelot_port_writel(ocelot->ports[port],
+					   DEV_CLOCK_CFG_LINK_SPEED
+					   (OCELOT_SPEED_1000),
+					   DEV_CLOCK_CFG);
 			break;
 		default:
 			dev_err(ocelot->dev,
-- 
1.9.1